LM5145 datasheet(18/55 Pages) TI

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the VCC setpoint level, the VCC output tracks VIN with a small voltage drop. Connect a ceramic decoupling

capacitor between 1 µF and 5 µF from VCC to AGND for stability.

The VCC regulator output has a current limit of 40 mA (minimum). At power up, the regulator sources current

into the capacitor connected to the VCC pin. When the VCC voltage exceeds its rising UVLO threshold of 4.93

V, the output is enabled (if EN/UVLO is above 1.2 V), and the soft-start sequence begins. The output remains

active until the VCC voltage falls below its falling UVLO threshold of 4.67 V (typical) or if EN/UVLO goes to a

standby or shutdown state.

Internal power dissipation of the VCC regulator can be minimized by connecting the output voltage or an

auxiliary bias supply rail (up to 13 V) to VCC using a diode DVCC as shown in Figure 8-2. A diode in series with

the input prevents reverse current flow from VCC to VIN if the input voltage falls below the external VCC rail.

VCC

LM5146

VIN

VCC-EXT

Required if VIN < VCC(EXT)

CVIN

0.1 PF

DVIN

VIN

CVCC

2.2 PF

DVCC

8 V to 13 V

AGND

5.5 V to 100 V

Figure 8-2. VCC Bias Supply Connection From VOUT or Auxiliary Supply

Note that a finite bias supply regulator dropout voltage exists and is manifested to a larger extent when driving

high gate charge (QG) power MOSFETs at elevated switching frequencies. For example, at VVIN = 6 V, the VCC

voltage is 5.8 V with a DC operating current, IVCC, of 20 mA. Such a low gate drive voltage can be insufficient

to fully enhance the power MOSFETs. At the very least, MOSFET on-state resistance, RDS(ON), can increase at

such low gate drive voltage.

Here are the main considerations when operating at input voltages below 7.5 V:

• Increased MOSFET RDS(on) at lower VGS, leading to Increased conduction losses and reduced OCP setpoint

• Increased switching losses given the slower switching times when operating at lower gate voltages

• Restricted range of suitable power MOSFETs to choose from (MOSFETs with RDS(on) rated at VGS = 4.5 V

become mandatory)

8.3.4 Precision Enable (EN/UVLO)

The EN/UVLO input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed by

the resistor values for application specific power-up and power-down requirements. EN/UVLO connects to a

comparator-based input referenced to a 1.2-V bandgap voltage. An external logic signal can be used to drive the

EN/UVLO input to toggle the output ON and OFF and for system sequencing or protection. The simplest way

to enable the operation of the LM5146 is to connect EN/UVLO directly to VIN. This allows self start-up of the

LM5146 when VCC is within its valid operating range. However, many applications benefit from using a resistor

divider RUV1 and RUV2 as shown in Figure 8-3 to establish a precision UVLO level.

Use Equation 1 and Equation 2 to calculate the UVLO resistors given the required input turn-on and turn-off

voltages.

IN(on)

IN(off)

UV1

HYS

(1)

LM5146

SNVSBV0A – JUNE 2021 – REVISED JUNE 2021

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