LM5145 datasheet(49/55 Pages) TI

49 / 55 page

2. Place all sensitive analog traces and components such as COMP, FB, RT, ILIM, and SS/TRK away from

high-voltage switching nodes such as SW, HO, LO, or BST to avoid mutual coupling. Use an internal layer or

layers as a ground plane or ground planes. Pay particular attention to shielding the feedback (FB) trace from

power traces and components.

3. The upper feedback resistor can be connected directly to the output voltage sense point at the load device or

the bulk capacitor at the converter side.

4. Connect the ILIM setting resistor from the drain of the low-side MOSFET to ILIM and make the connections

as close as possible to the LM5146. The trace from the ILIM pin to the resistor must avoid coupling to a

high-voltage switching net.

5. Minimize the loop area from the VCC and VIN pins through their respective decoupling capacitors to the

GND pin. Locate these capacitors as close as possible to the LM5146.

11.1.4 Thermal Design and Layout

The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO

regulator is greatly affected by:

• Average gate drive current requirements of the power MOSFETs

• Switching frequency

• Operating input voltage (affecting bias regulator LDO voltage drop and hence its power dissipation)

• Thermal characteristics of the package and operating environment

For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient

removal of the heat produced while keeping the junction temperature within rated limits. The LM5146 controller

is available in a small 3.5-mm × 4.5-mm 20-pin VQFN (RGY) PowerPAD™ package to cover a range of

application requirements. The thermal metrics of this package are summarized in Section 7.4. The application

report Semiconductor and IC Package Thermal Metrics provides detailed information regarding the thermal

information table.

The 20-pin VQFN package offers a means of removing heat from the semiconductor die through the exposed

thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any

leads of the package, it is thermally connected to the substrate of the LM5146 device (ground). This allows a

significant improvement in heat sinking, and it becomes imperative that the PCB is designed with thermal lands,

thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the LM5146 is

soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the

thermal resistance to a very low value. Wide traces of the copper tying in the no-connect pins of the LM5146

(pins 9 and 16) and connection to this thermal land helps to dissipate heat.

Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal and solder-side ground

plane(s) are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed on the

PCB layer below the power components. Not only does this provide a plane for the power stage currents to flow

but it also represents a thermally conductive path away from the heat generating devices.

The thermal characteristics of the MOSFETs also are significant. The drain pad of the high-side MOSFET is

normally connected to a VIN plane for heat sinking. The drain pad of the low-side MOSFET is tied to the SW

plane, but the SW plane area is purposely kept relatively small to mitigate EMI concerns.

11.1.5 Ground Plane Design

As mentioned previously, using one or more of the inner PCB layers as a solid ground plane is recommended.

A ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for

the control circuitry. Connect the PGND pin to the system ground plane using an array of vias under the exposed

pad. Also connect the PGND directly to the return terminals of the input and output capacitors. The PGND net

contains noise at the switching frequency and can bounce because of load current variations. The power traces

for PGND, VIN and SW can be restricted to one side of the ground plane. The other side of the ground plane

contains much less noise and is ideal for sensitive analog trace routes.

www.ti.com

LM5146

SNVSBV0A – JUNE 2021 – REVISED JUNE 2021

Submit Document Feedback

Product Folder Links: LM5146

LM5145 датащи(PDF) 49 Page - Texas Instruments

LM5145 датащи(HTML) 49 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

датащи скачать

ссылки URL