FUSB3307

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15

USB 2.0 Data Lines

The USB 2.0 Data Lines D+ and D− can be externally

connected together via a 100 ohms resistor to provide the

maximum power, a legacy USB device can take, which is

1.5 A per USB Battery Charging v1.2 (BC1.2) specification.

This will usually be the case when a USB−C to micro−B

cable is plugged into this design where this adapter cable has

the required Sink Rd resistors within it to allow the

FUSB3307 to recognize a Type C attach and to source 5 V

on VBUS. The Sink will go through BC1.2 steps of primary

and secondary detection to detect a Dedicated Charging Port

(DCP) via this resistor connection of D+ and D− and takes

1.5 A maximum from VBUS.

If selected by the Trim table (Table 6), to attach to certain

phones that require resistor dividers on D+ and D− then

connect D+ and D− to the FUSB3307 with small (22

W

typical) resistors which auto−detects which type of legacy

Sink is plugged in and automatically provides the legacy

device with the appropriate power level it needs to charge.

Note this power level is controlled by the device itself not the

power source which is typical of most legacy USB power

systems. The FUSB3307 will allow for 5 V at a maximum

of 3 A for even legacy devices which will take at most either

1.5 A or 2.4 A for most legacy devices.

D+ and D− can also be connected to a USB Physical Layer

(PHY) controller for using these lines for data traffic. In that

case, the USB PHY is expected to advertise itself as a

Charging Downstream Port (CDP) per BC1.2 so that the

Sink can take a maximum of 1.5 A of power.

D+ and D− are low voltage pins (6 V absolute maximum

voltage) and are not expected to be shorted to VBUS when

VBUS goes higher than 6 V. The TVS diodes connected to

D+ and D− shown in the figure (ESD7104) allow operating

voltages up to 5 V for the offline design (Figure 5) and

typically D+ and D− are 3.3 V signals when used for USB

2.0 data signals. For the automotive buck−boost design

(Figure 6), short−to−VBUS protection is shown via the

NIV1241 that contain TVS diodes and FETs to keep the

FUSB3307 D+ and D− lines less than 5 V as shown in

Figure 13.

Figure 13. D+ and D− Pin Protection Provided by the

NIV1241

Power Delivery Operation

FUSB3307 advertises source capabilities and responds to

PD message completely autonomously following the USB

PD 3.0 with PPS and Type C specifications. For more details

on the USB PD messages please refer to the specification

references mentioned below (See Specification References

on page 19). Similarly the references mention the Type C

and the BC1.2 specifications as well for further information.

To allow for a variety of designs, the following table has

a number of trim options to accommodate almost every

design. The following Table 6 lists out the various options.

While all these options exist, they can only be obtained from

ON Semiconductor if requested and once delivered, the trim

option cannot be changed. The default trim option column

below is for a 60 W design that uses 3 A cables and is for a

USB Power Delivery (PD) 3.0 design with Programmable

Power Supplies (PPS) and Fixed Supplies. In the future

more default options will be available for general purpose

use with likely 30 W, 45 W and 90 W power levels in

addition to the 60 W option.

Table 6. FUSE TRIM (NOTE 7) OPTION TABLE

#

Function

Trim Option

Default Option

1

Output Power

PD Power (PDP) from 16 W to 100 W in 1W increments

60 W

2

Cable Compensation

Four choices of 50 mV/A, 100 mV/A, 150 mV/A and Disabled

Disabled

3

5 A Power Source

0 = Max current is 3 A, no eMarker detection

1 = Max current is 5 A, eMarker detection needed

0 = Max current = 3 A,

no eMarker detection

4

Charging Output OVP

Four choices of OVP thresholds: 115%, 120%, 125% and 130%

120% OVP

5

Charging Output UVP

Four choices of UVP thresholds: 60%, 65%, 70% and Disabled

65% UVP

6

D+/D− versus

PDIV0/PDIV1

00: D+/PDIV1=D+, D−/PDIV0=D− (SOIC package without PDIV2 pin)

01: D+/PDIV1=PDIV1, D−/PDIV0=PDIV0 (SOIC package without PDIV2 pin)

10: D+/PDIV1=PDIV1, D−/PDIV0=PDIV0 PDIV2 standalone pin

(QFN package)

11: D+/PDIV1=D+, D−/PDIV0=D− PDIV2 standalone pin (QFN package)

00 for SOIC package

11 for QFN package

7

Support PD 3.0

0 = Enable PD 2.0

1 = Enable PD 3.0

1 = Enable PD 3.0

7. ”Trim Options” means feature programmability to create new functional options in a manufacturing test program by trimming semiconductor

fuses.