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FUSB251 датащи(PDF) 7 Page - ON Semiconductor

номер детали FUSB251
подробное описание детали  Type-C CC and SBU Protection IC
PDF  19 Pages
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производитель  ONSEMI [ON Semiconductor]
домашняя страница  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

FUSB251 датащи(HTML) 7 Page - ON Semiconductor

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ELECTRICAL SPECIFICATION TABLE Unless otherwise specified: Recommended TA and TJ temperature ranges. All typical
values are at TA = 25°C and VDD = 3.8 V unless otherwise specified.
Symbol
Unit
Max
Typ
Min
Conditions
Parameter
CON_SBU
SBU Switch ON capacitance (Note 1)
VDD = 2.7 to 5.5 V, Capacitance
from SBUx or SBUx_H to GND.
Switch closed, VSW = 0 − VDD,
25
pF
BWCC
CC channel bandwidth (Note 1)
VDD = 3.6 V, −3 dB bandwidth,
RL = 50 W, CL = 200 pF
25
MHz
BWSBU
SBU switch Bandwidth (Note 1)
VDD = 3.6 V, −3 dB bandwidth
between SBUx and SBUx_H.
Singled ended, RL = 50 W
30
MHz
TCC_MOS
Timer of CC moisture detection (Note 1)
VDD = 2.7 to 5.5 V,
Timer for searching both CC rise.
Timer reset at both CC rising.
108
120
132
ms
TDRY
Dry check period (Note 1)
VDD = 2.7 to 5.5 V, Timer period of
SBU moisture detection for Dry
check, Programmable
0.1
10
s
TSBU_PRD
Time between SBU1 and SBU2 mois-
ture detection (Note 1)
VDD = 2.7 to 5.5 V, SBU moisture
detection enabled and measure
time voltage source on from SBU1
to SBU2
0.9
1.0
1.1
ms
VCC_RISE_MOS
Moisture detection start voltage when
both CC1 and CC2 rise
VDD = 2.7 to 5.5 V
130
200
270
mV
VOUTL_INTB
INTB output Low voltage
VDD = 2.7 to 5.5 V
0.4
V
VIH_I2C
SDA, SCL High level input voltage
VDD = 2.7 to 5.5 V
1.2
V
VHYS_I2C
SDA, SCL Hysteresis of Schmitt Trigger
Inputs
VDD = 2.7 to 5.5 V
200
mV
II2C
Input Current of SDA and SCL Pins
VDD = 2.7 to 5.5 V,
Input Voltage 0 to VDD
−0.5
0.5
mA
ICCT_I2C
VDD current when SDA or SCL is HIGH Input voltage is 1.8 V
−0.5
2.5
mA
VOL_SDA
Low−Level Output Voltage
VDD = 2.7 to 5.5 V, 2 mA sink cur-
rent, Pull up to VDD
0
0.3
V
CI2C
Capacitance on SDA and SCL (Note 1)
VDD = 2.7 to 5.5 V
10
pF
f_SCL
I2C SCL clock frequency
400
kHz
tHD ; STA
Hold Time (Repeated) START Condition
0.6
ms
tLOW
LOW Period of I2C_SCL Clock
1.3
ms
tHIGH
High Period of I2C_SCL Clock
0.6
ms
tSU ; STA
Set−up Time for Repeated START
Condition
0.6
ms
tHD ; DAT
Data Hold Time
0
0.9
ms
tSU ; DAT
Data Set−up Time
100
ns
tR
Rise Time of I2C_SDA and I2C_SCL
Signals
20 ×
(VDD/5.5 V)
250
ns
tF
Fall Time of I2C_SDA and I2C_SCL
Signals
20×
(VDD/5.5 V)
250
ns
tSU ; STO
Set−up Time for STOP Condition
0.6
ms
tBUF
BUS−Free Time between STOP and
START Conditions
1.3
ms
tSP
Pulse Width of Spikes that Must Be
Suppressed by the Input Filter
0
50
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by Design, Characterization, not Production tester.



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