ADRV9002BBCZ datasheet(17/92 Pages) AD

17 / 92 page

Data Sheet

ADRV9002

SPECIFICATIONS

analog.com

Rev. 0 | 17 of 92

Table 10. LTE40 One Transmitter and One Receiver (1T1R), LO = 2.5 GHz, High Performance Clock PLL, LVDS SSI

ADRV9002 Mode Conditions

Supply (mA)

Total

Average

Power (W)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

1 × Transmitter RF Attenuation = 0 dB, Full-Scale Continuous Wave 40 MHz

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Disabled,

QEC Engine Inactive, and Receiver in Primed State

Not used

140

486

143

1.080

1 × Transmitter RF Attenuation = 10 dB, Full-Scale Continuous Wave

40 MHz Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC

Disabled, QEC Engine Inactive, and Receiver in Primed State

Not used

141

486

0.942

1 × Transmitter RF Attenuation = 0 dB, Full-Scale Continuous Wave 40 MHz

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Enabled,

QEC Engine Active, Receiver in Primed State, Transmitter QEC Tracking

Always On, Observation Receiver Continuously On, and Transmitter Tracking

is Duty Cycled (Practical Scenario)

Not used

232

754

156

1.543

1 × Transmitter RF Attenuation = 10 dB, Full-Scale Continuous Wave

40 MHz Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC

Enabled, QEC Engine Active, Receiver in Primed State, Transmitter QEC

Tracking Always On, Observation Receiver Continuously On, and Transmitter

Tracking is Duty Cycled (Practical Scenario)

Not used

231

755

1.405

FDD Operation

Transmit channel enabled, 40 MHz transmitter bandwidth, 61.44 MSPS data rate, transmitter internal LO = 2.4 GHz, transmit QEC disabled,

QEC engine inactive, LVDS SSI. Receive channel enabled, 40 MHz receiver bandwidth, 61.44 MSPS data rate, receiver internal LO = 2.5 GHz,

high performance clock PLL, high performance receiver ADC low rate, receive QEC enabled, and QEC engine active. Using a low power ADC

decreases power consumption by approximately 110 mW per receiver channel. No auxiliary DACs or auxiliary ADCs are enabled.

Table 11. FDD Modes

ADRV9002 Mode Conditions

Supply (mA)

Total Average

Power (W)

VDDA_1P0 Analog

Supplies

VDD_1P0 Digital

Supply

VDDA_1P3 Analog

Supplies

VDDA_1P8 Analog

Supplies

VDD_1P8 Digital

Supply

1 × Receiver, 1 × Transmitter RF

Attenuation = 0 dB, Full-Scale Continuous

Wave

Not used

298

835

179

1.756

1 × Receiver, 1 × Transmitter

RF Attenuation = 10 dB, Full-Scale

Continuous Wave

Not used

298

835

103

1.619

2 × Receiver, 2 × Transmitter RF

Attenuation = 0 dB, Full-Scale Continuous

Wave

Not used

507

1234

344

2.826

2 × Receiver, 2 × Transmitter

RF Attenuation = 10 dB, Full-Scale

Continuous Wave

Not used

507

1234

190

2.549

TIMING SPECIFICATIONS

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SERIAL PERIPHERAL INTERFACE (SPI) TIMING

tCP

SPI_CLK period, 3-wire mode

SPI_CLK period, 4-wire mode

tMP

SPI_CLK pulse width

tSC

SPI_EN setup to first SPI_CLK rising edge

ADRV9002BBCZ датащи(PDF) 17 Page - Analog Devices

ADRV9002BBCZ датащи(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

датащи скачать

ссылки URL