ADRV9002BBCZ datasheet(14/92 Pages) AD

14 / 92 page

Data Sheet

ADRV9002

SPECIFICATIONS

analog.com

Rev. 0 | 14 of 92

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL SPECIFICATIONS (DIGITAL

GPIO SIGNALS)

Logic Inputs

Input Voltage

High Level

VDIGIO_1P8 ×

0.65

VDIGIO_1P8 +

0.18

Low Level

−0.30

VDIGIO_1P8 ×

0.35

Logic Outputs

Output Voltage

High Level

VDIGIO_1P8 −

0.45

Low Level

0.45

Drive Capability

DATAPORT SPECIFICATIONS (LVDS

SSI, MCS+ and MCS−)

Logic Inputs

Input Voltage Range

825

1675

Each differential input in the pair

Input Differential Voltage

Threshold

−100

+100

Receiver Differential Input

Impedance

100

Internal termination enabled

Logic Outputs

Output Voltage

High Level

1390

Low Level

1000

Differential

300

Offset

1200

Drivers are shorted to ground, there is no internal termination

available, an off-chip 100 Ω termination is required

Output Current

4.1

Drivers are shorted together

Clock Signal Duty Cycle

500 MHz

Output Rise and Fall Time

0.371

300 mV p-p swing

DIGITAL SPECIFICATIONS (ANALOG

GPIO SIGNALS)

Logic Inputs

Input Voltage

High Level

VDDA_1P8 × 0.65

VDDA_1P8 + 0.18 V

Low Level

−0.30

VDDA_1P8 × 0.35 V

Logic Outputs

Output Voltage

High Level

VDDA_1P8 − 0.45

Low Level

0.45

Drive Capability

1 VDDA_1P8 refers to all analog 1.8 V supplies including VCONV_1P8, VAGPIO_1P8, VANA2_1P8, and VANA1_1P8.

ADRV9002BBCZ датащи(PDF) 14 Page - Analog Devices

ADRV9002BBCZ датащи(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

датащи скачать

ссылки URL