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ADRF6720ACPZ-R7 датащи(PDF) 40 Page - Analog Devices

номер детали ADRF6720ACPZ-R7
подробное описание детали  Wideband Quadrature Modulator with Integrated Fractional-N PLL and VCOs
PDF  44 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADRF6720ACPZ-R7 датащи(HTML) 40 Page - Analog Devices

Back Button ADRF6720ACPZ-R7 Datasheet HTML 36Page - Analog Devices ADRF6720ACPZ-R7 Datasheet HTML 37Page - Analog Devices ADRF6720ACPZ-R7 Datasheet HTML 38Page - Analog Devices ADRF6720ACPZ-R7 Datasheet HTML 39Page - Analog Devices ADRF6720ACPZ-R7 Datasheet HTML 40Page - Analog Devices ADRF6720ACPZ-R7 Datasheet HTML 41Page - Analog Devices ADRF6720ACPZ-R7 Datasheet HTML 42Page - Analog Devices ADRF6720ACPZ-R7 Datasheet HTML 43Page - Analog Devices ADRF6720ACPZ-R7 Datasheet HTML 44Page - Analog Devices  
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ADRF6720
Data Sheet
Table 28. Bit Descriptions for PFD_CP_CTL
Bits
Bit Name
Settings
Description
Reset
Access
[6:5]
ABLDLY
Set Antibacklash Delay.
0x0
RW
00
0 ns.
01
0.5 ns.
10
0.75 ns.
11
0.9 ns.
[4:2]
CP_CTRL
Set Charge Pump Control.
0x4
RW
000
Both On.
001
Pump Down.
010
Pump Up.
011
Tristate.
100
PFD.
[1:0]
PFD_CLK_EDGE
Set PFD Clock Edge Trigger.
0x0
RW
00
Divide and Reference Down Edge.
01
Divide Down Edge, Reference Up Edge.
10
Divide Up Edge, Reference Down Edge.
11
Divide and Reference Up Edge.
Address: 0x42, Reset: 0x000E, Name: DITH_CTL1
Table 29. Bit Descriptions for DITH_CTL1
Bits
Bit Name
Settings
Description
Reset
Access
3
DITH_EN
Set Dither Enable.
0x1
RW
0
Disable.
1
Enable.
[2:1]
DITH_MAG
Set Dither Magnitude.
0x3
RW
0
DITH_VAL
Set Dither Value.
0x0
RW
Address: 0x43, Reset: 0x0000, Name: DITH_CTL2
Table 30. Bit Descriptions for DITH_CTL2
Bits
Bit Name
Settings
Description
Reset
Access
[15:0]
DITH_VAL
Set Dither Value.
0x0
RW
Rev. 0 | Page 40 of 44



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