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ADGS1208BCPZ датащи(PDF) 25 Page - Analog Devices |
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ADGS1208BCPZ датащи(HTML) 25 Page - Analog Devices |
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25 / 33 page ![]() Data Sheet ADGS1208/ADGS1209 Rev. 0 | Page 25 of 33 ROUND ROBIN MODE Round robin mode allows the ADGS1208/ADGS1209 to cycle through the channels faster by reducing the overhead needed from the digital interface to switch from one channel to the next. The round robin configuration register selects which channels are to be included in a cycle, while the CNV edge select register selects on which edge of CNV the ADGS1208/ ADGS1209 switch to the next channel in the sequence. At the end of the channel cycle, a resync pulse appears on SDO to inform the user that the current cycle ended and then it loops back to the start of the sequence of channels. Figure 52 shows an example of the round robin mode interface and Figure 53 shows the CNV signal of the analog-to-digital converter (ADC) being used in conjunction with the ADGS1208 in round robin mode. After configuration completes, the round robin enable register allows the ADGS1208/ADGS1209 to enter round robin mode. When in round robin mode, the SPI is no longer used to switch between channels. Instead, to switch from one channel to another, ensure that a digital signal is present on the CNV pin while CS is pulled low. To exit round robin mode, either perform a hardware reset or send the 16-bit addressable mode SPI frames: 0xA318 followed by 0xE3B4. These are the only SPI commands recognized by the SPI interface while in round robin mode. Round robin mode is significantly faster than addressable mode to cycle through channels because it removes the 16-bit overhead required to change input channel. In addition, round robin mode removes the need for SCLK to be running, which reduces the digital current consumption (IL). The maximum CNV frequency is bound by the transition time of the device, along with the required settling time for the application. CNV MUX CHANNEL X S1 S2 S(LAST) ROUND ROBIN CYCLE SDO RESYNC CS Figure 52. Round Robin Mode Interface Example CNV AQUISITION AQUISITION tACQ tCYC tCONV tDIS tEN CONVERSION SCK SDO MUX CHANNEL D15 D14 N + 2 N + 1 N D13 D1 D0 1 2 3 14 15 16 AD7980 SDO SDI SDI DATA IN DIGITAL HOST CLK VIO CNV SCK CONVERT IN0 IN1 IN2 IN7 ADGS1208 SCK CS GPO GPO CNV D IN S1 S2 S8 S3 Figure 53. Example of CNV Signal of an ADC Cycling Through Channels in the ADGS1208 |
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