LTC4380 datasheet(17/24 Pages) AD

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LTC4381

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Figure 6. Design Example 1: 12V/1A Application Survives 100V, 2ms OV Transient

Design Example 1

As a design example, take an application with the follow-

ing specifications: VIN = 10V to 14VDC with a transient

of 100V and duration of 2ms, VOUT ≤ 20V and cold crank

to 3V for 40ms. Maximum load of 1A.

To clamp VOUT to less than 20V, the required VCC clamp

is given by Equation 13.

VCC (Clamp) = VOUT – 10.5V

= 20V – 10.5V = 9.5V

(13)

The selection of a 7.5V Zener diode for D1 limits the

voltage at the VOUT to less than 20V during a 100V surge.

The minimum required voltage at the VCC pin is 4V when

VIN is at 10V; the VCC pin input current is less than 30μA.

The maximum value for R1 to ensure proper operation is

given by Equation 14.

R1=

Min VIN – Min VCC

Supply Current

10V – 4V

30µA

= 200kΩ (14)

We used R1 of 100k to cover all condition.

The maximum current through R1 into D1 during tran-

sients is then calculated using Equation 15.

ID1 =

100V – 7.5V

100kΩ

= 0.925mA

(15)

CMHZ5236B can handle 500mW indefinitely and 1W for 1

second. The VCC pin needs at least 4V to operate through

cold crank from 12V down to 3V for 40ms. The value of

C1 can be calculated by Equation 16.

C1 =

–40ms

100kΩ •In (4.5)

= 0.266µF

(16)

0.33μF is chosen to accommodate for the supply current

of the part and other conditions. With C1 = 0.33μF and

R1 = 100kΩ, high voltage transients up to 100V with a

pulse width of less than 2ms are filtered out at the VCC

pin. Longer surges are suppressed by D1.

RDRN is chosen to produce a current into the DRN pin of

1mA, during the maximum overvoltage transient event

(Equation 17). VOUT is clamped to 7.5V + 10.5V or 18V.

RDRN =

100V – 18V

1mA

= 82kΩ

(17)

82.5kΩ is chosen as the next bigger value. The GATE pin

pull-up current is 20µA typically, it takes a while to pull

the GATE pin high during input transient. So the MOSFET

sees a larger VDS initially and the worst case P√t occur

RSNS

40m

100k

RDRN

82.5k

0.33µF

CTMR

220nF

47nF

COUT

22µF

7.5V

DRN

VCC

SEL

GND

4381 F06

TMR

SRC

SNS

OUT

LTC4381-4

GATE

GFET

VIN

12V

FLT

12V/1A OUTPUT

CLAMPED AT 20V

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