LTM4657 datasheet(22/28 Pages) AD

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LTM4657

Rev. A

For more information www.analog.com

APPLICATIONS INFORMATION

Table 7. Output Voltage Response vs Component Matrix (Refer to Figure 23)

COUT1

PART NUMBER

VALUE

COUT2

PART NUMBER

VALUE

Murata

GRM31CR60J107M

100µF, 6.3V, 1206, X5R

Murata

GRM31CR71A226K

22µF, 10V, 1206, X7R

VIN

(V)

VOUT

(V)

fSW

(kHz)

COUT1

(CER CAP)

COUT2

(CER CAP)

COMPENSATION

CFF

(pF)

LOAD STEP

(A)

LOAD STEP

SLEW RATE

(A/µs)

P-P

DEVIATION

(mV)

RECOVERY

TIME

(µs)

500

2× 100µF

22µF

Internal, COMPa = COMPb

100

0 - 2

500

2× 100µF

22µF

Internal, COMPa = COMPb

100

0 - 2

1.5

650

2× 100µF

22µF

Internal, COMPa = COMPb

100

0 - 2

1.5

650

2× 100µF

22µF

Internal, COMPa = COMPb

100

0 - 2

2.5

800

2× 100µF

22µF

Internal, COMPa = COMPb

100

0 - 2

2.5

800

2× 100µF

22µF

Internal, COMPa = COMPb

100

0 - 2

3.3

1000

2× 100µF

22µF

Internal, COMPa = COMPb

100

0 - 2

3.3

1000

2× 100µF

22µF

Internal, COMPa = COMPb

100

0 - 2

107

1250

2× 100µF

22µF

Internal, COMPa = COMPb

100

0 - 2

142

VIN

VOUT

4657 F22

GND

Safety Considerations

The LTM4657 modules do not provide galvanic isolation

from VIN to VOUT. There is no internal fuse. If required,

a slow blow fuse with a rating twice the maximum input

current needs to be provided to protect each unit from

catastrophic failure. The device does support thermal

shutdown and over current protection.

Layout Checklist/Example

The high integration of LTM4657 makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout consid-

erations are still necessary.

• Use large PCB copper areas for high current paths,

including VIN, GND and VOUT. It helps to minimize the

PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capac-

itors next to the VIN, PGND and VOUT pins to minimize

high frequency noise.

• Place a dedicated power ground layer underneath

the unit.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Do not put via directly on the pad, unless they are

capped or plated over.

• Bring out test points on the signal pins for monitoring.

• Keep separation between CLKIN, CLKOUT and FREQ

pin traces to minimize possibility of noise due to cross-

talk between these signals.

Figure 22givesagoodexampleoftherecommended layout.

Figure 22. Recommended PCB Layout

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