MCP6C04 datasheet(36/54 Pages) MICROCHIP

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MCP6C04

DS20006179A-page 36

 2019 Microchip Technology Inc.

5.0

APPLICATIONS

This chapter includes design recommendations and

typical application circuits.

The Common-mode rejection (see Figure 2-13,

Figure 2-14, Figure 2-15 and Figure 2-42) supports

applications in noisy environments. Our Current-mode

architecture gives high CMRR at higher frequencies

than was traditional (e.g., 80 dB near 80 kHz, instead

of near 60 Hz).

The power supply rejection (see Figure 2-43) also has

excellent rejection at higher frequencies than

traditional.

5.1

Recommended Design Practices

Some simple design practices help take advantage of

the MCP6C04's performance in high-side current

sensing applications.

5.1.1

INPUT VOLTAGE LIMITS

To prevent damage and/or improper operation of these

amplifiers, the circuit must limit the voltages at the VIP

and VIM input pins, as well as the differential input

voltage VDM (see Section 1.1, Absolute Maximum

Ratings †). These requirements are independent of

the current limits discussed below.

The ESD protection on the VIP and VDM inputs was

discussed in Section 4.3.1, Internal Protection

Devices. This structure was chosen to protect the input

transistors against many (but not all) overvoltage

conditions, and to minimize input bias currents (IBP and

IBM).

To protect the inputs, always drive VIP with a low

impedance source and use a shunt resistor (RSH) with

low resistance (designed to not fail open). Placing

zener diode(s) or a transorb across RSH will also help

protect the inputs.

5.1.2

INPUT CURRENT LIMITS

To prevent damage to (or improper operation of) these

amplifiers, the circuit must limit the currents into the VIP

and VIM input pins (see Section 1.1, Absolute

Maximum

Ratings †).

This

requirement

independent of the voltage limits discussed above.

One way to ensure the input currents are limited is to

always drive VIP with a low impedance source, and to

use a shunt resistor (RSH) with low resistance

(designed to not fail open). Placing zener diode(s) or a

transorb across RSH will also help protect the inputs.

5.1.3

BYPASS CAPACITORS

Be sure to specify capacitors that will support your

application. Be sure to look at:

• Voltage rating (well above the maximum value for

its pins)

• Dielectrics (good Temp. Cos. and reasonable

Volt. Cos.

•Size

• Surface mount vs. leaded

• Cost vs. availability

If possible, connect VSS to ground. This will make your

design simpler.

Bypass VIP to VSS with a local bypass capacitor next to

these pins (e.g.,10 nF). If needed, a bulk bypass

capacitor can also be added (e.g.,1 µF).

Bypass VDD to VSS with a local bypass capacitor next

to these pins (e.g.,100 nF). A bulk bypass capacitor

should also be added close by (e.g.,2.2 µF); placing it

next to the local bypass capacitor is a good choice.

5.1.4

SETTING THE VOLTAGES AT VIP

AND VIM

VIP is tied to a voltage source, to minimize glitches and

crosstalk.

This

part’s

excellent

CMRR

versus

frequency helps reject Common-mode (i.e., at VIP)

noise and glitches. A local pass capacitor to VSS can

help, when the design allows it; 10 nF is usually a good

choice (see the Typical Application Circuit on Page 1).

A shunt resistor (RSH) is connected between VIP and

VIM, then to the load (which is grounded). It is selected

for the trade-off between accuracy (high RSH) and

power dissipation (low RSH). Low power dissipation

also leads to reduced size and cost. RSH also helps

protect these pins against large glitches; make sure it

will never fail open.

Bypass capacitors on VIP and VIM can reduce the risk

of high over-voltage events when the current changes

abruptly, such as an inductive load opening.

A good layout is necessary to minimize DC and AC

errors. Figure 5-1 shows a layout that minimizes input

resistances seen by IBN and IBM. The critical paths are

between RSH and the pins VIP and VIM (RWIP and

RWIM).

FIGURE 5-1:

PCB Layout for RSH

(connections to VIP and VIM).

Pin VIM

(trace = RWIM)

Pin VIP

trace to VHV

RSH

trace to load

(trace = RWIP)

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