6

ICS950818

0825F—11/19/03

Pin #

Name

0

1

PWD

Bit 7

34

48MHz_DOT

Output control

RW

Disable

Enable

1

Bit 6

35

48MHz_USB

Output control

RW

Disable

Enable

1

Bit 5

6

PCICLK_F2/PCICLK8 (see

note)

Allow control of output with

assertion of PCI_STOP#.

RW

Freerun

Not

Freerun

0

Bit 4

5

PCICLK_F1/PCICLK7 (see

note)

Allow control of output with

assertion of PCI_STOP#.

RW

Freerun

Not

Freerun

0

Bit 3

4

PCICLK_F0/PCICLK6 (see

note)

Allow control of output with

assertion of PCI_STOP#.

RW

Freerun

Not

Freerun

0

Bit 2

6

PCICLK_F2/PCICLK8

Output control

RW

Disable

Enable

1

Bit 1

5

PCICLK_F1/PCICLK7

Output control

RW

Disable

Enable

1

Bit 0

4

PCICLK_F0/PCICLK6

Output control

RW

Disable

Enable

1

Note:

Pin #

Name

0

1

PWD

Bit 7

10

*PCICLK2

Output strength (1X/2X)

R/W

2X

1X

1

Bit 6

12

*PCICLK3

Output strength (1X/2X)

R/W

2X

1X

1

Bit 5

29

PCICLK10

Output control

RW

Disable

Enable

1

Bit 4

31

3V66_1/VCH_CLK

Output control

RW

Disable

Enable

1

Bit 3

20

PCICLK9

Output control

RW

Disable

Enable

1

Bit 2

19

3V66_4

Output control

RW

Disable

Enable

1

Bit 1

18

3V66_3

Output control

RW

Disable

Enable

1

Bit 0

17

3V66_2

Output control

RW

Disable

Enable

1

Pin #

Name

0

1

PWD

Bit 7

X

PD Mode Iref Mirror Enable

Allow Iref Mirror to be ON during

Power Down Mode

RW

OFF

ON

0

Bit 6

X

Reserved

Reserved

X

-

-

0

Bit 5

X

3V66(4:2) (See table 6)

Allow control of output with

assertion of CPU_STOP#.

X

Freerun

Not

Freerun

0

Bit 4

X

3V66(1) (See table 7)

Allow control of output with

assertion of CPU_STOP#.

X

Freerun

Not

Freerun

0

Bit 3

RW

-

-

0

Bit 2

RW

-

-

0

Bit 1

RW

-

-

0

Bit 0

RW

-

-

0

Note:

PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 4.

Control Function

00 = Medium (default), 01 = Low,

11,10 =High

Bit Control

Bit Control

BYTE

3

Control Function

Affected Pin

Bit Control

Type

BYTE

4

Affected Pin

BYTE

5

Type

Control Function

Affected Pin

Type

34

48MHz_DOT Slew Control

48MHz_USB Slew Control

35

Functions in Byte 5 of CK408 were intended as a test and debug byte only.

00 = Medium (default), 01 = Low,

11,10 =High