2

ICS950818

0825F—11/19/03

Pin Description

PIN # PIN NAME

PIN TYPE

DESCRIPTION

1

X1

IN

Crystal input, Nominally 14.318MHz.

2

X2

OUT

Crystal output, Nominally 14.318MHz

3

GND

PWR

Ground pin.

4

PCICLK_F0/PCICLK6

OUT

Free running/Non-Free running PCI clock selected by SMBus.

5

PCICLK_F1/PCICLK7

OUT

Free running/Non-Free running PCI clock selected by SMBus.

6

PCICLK_F2/PCICLK8

OUT

Free running/Non-Free running PCI clock selected by SMBus.

7

GND

PWR

Ground pin.

8

PCICLK0

OUT

PCI clock output.

9

PCICLK1

OUT

PCI clock output.

10

*PCICLK2

OUT

PCI clock output.

11

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

12

*PCICLK3

I/O

PCI clock output.

13

PCICLK4

OUT

PCI clock output.

14

PCICLK5

OUT

PCI clock output.

15

VDD3V66

PWR

Power pin for the 3V66 clocks.

16

GND

PWR

Ground pin.

17

3V66_2

OUT

3.3V 66.66MHz clock output

18

3V66_3

OUT

3.3V 66.66MHz clock output

19

3V66_4

OUT

3.3V 66.66MHz clock output

20

PCICLK9

OUT

PCI clock output.

21

PD#

IN

Asynchronous active low input pin used to power down the device into a low

power state. The internal clocks are disabled and the VCO and the crystal

are stopped.

22

VDDA

PWR

3.3V power for the PLL core.

23

GND

PWR

Ground pin.

24

Vtt_PWRGD#

IN

This 3.3V LVTTL input is a level sensitive strobe used to determine when

latch inputs are valid and are ready to be sampled. This is an active low

input.