LTM8083

15

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Figure 6. Graphical Approximation of the Thermal Coefficients, Including JESD 51-12 Terms

8083 F06

µMODULE DEVICE

(TOP) RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

CASE (BOTTOM)-TO-BOARD

RESISTANCE

Within the LTM8083, be aware that there are multi-

ple power devices and components dissipating power,

with a consequence that the thermal resistances rel-

ative to different junctions of components or die are

not exactly linear with respect to total package power

loss. To reconcile this complication without sacrificing

modeling simplicity—but also, not ignoring practical

realities—an approach has been taken using FEA soft-

ware modeling along with laboratory testing in a con-

trolled environment chamber to reasonably define and

correlate the thermal resistance values supplied in this

data sheet: (1) Initially, FEA software is used to accu-

rately build the mechanical geometry of the LTM8083

and the specified PCB with all of the correct material

coefficients along with accurate power loss source

definitions; (2) this model simulates a software-de-

fined JEDEC environment consistent with JESD51-

12 to predict power loss heat flow and temperature

readings at different interfaces that enable the calcu-

lation of the JEDEC-defined thermal resistance values;

(3) the model and FEA software is used to evaluate the

LTM8083 with heat sink and airflow; (4) having solved

for and analyzed these thermal resistance values and

simulated various operating conditions in the software

model, a thorough laboratory evaluation replicates the

simulated conditions with thermocouples within a

controlled environment chamber while operating the

device at the same power loss as that which was sim-

ulated. An outcome of this process and due diligence

yields the set of derating curves shown in this data

sheet. After these laboratory tests have been performed

provided assuming approximately 100% of power loss

flows from the junction through the board into ambient

with no airflow or top mounted heat sink.