LTM8083 datasheet(12/24 Pages) AD

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LTM8083

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

output ripple voltage. The maximum steady state ripple

due to charging and discharging the bulk capacitance is

given by:

ΔVCAP(BOOST) =

IoMAX • VOUT – VIN(MIN)

(

)

COUT • VOUT • fSW

ΔVCAP(BUCK) =

VOUT • VIN(MAX) – VOUT

(

)

8 •L • COUT • VIN(MAX) • fSW2

The maximum steady ripple due to the voltage drop

across the ESR is given by:

ΔVESR(BOOST) =

VOUT •IoMAX

VIN(MAX)

•ESR

ΔVESR(BUCK) =

VOUT • VIN(MAX) – VOUT

(

)

VIN(MAX) •L • fSW

•ESR

The bulk output capacitors defined as COUT are chosen

with low enough ESR to meet the output voltage ripple

and transient requirements. COUT can be the low ESR

tantalum capacitor, the low ESR polymer capacitor or

the ceramic capacitor. Multiple capacitors can be placed

in parallel to meet the ESR and RMS current handling

requirements. The typical capacitance is 10μF. Additional

output filtering may be required by the system designer,

if further reduction of output ripple or dynamic transient

spike is required. A 10nF low-ESL three-terminal capaci-

tor is integrated inside the module to decouple high-fre-

quency output noise. Table 6 shows a matrix of different

output voltages and output capacitors to minimize the

voltage droop and overshoot at a current transient.

INTVCC Regulator

An internal P-channel low dropout regulator produces

3.6V at the INTVCC pin from the SVIN supply pin. The

INTVCC powers internal circuitry and gate drivers in the

LTM8083. No bypassing capacitor is required.

Programming VIN UVLO and OVLO

A resistor divider from VIN to the EN/UVLO pin implements

VIN undervoltage lockout (UVLO). The EN/UVLO enable

falling threshold is set at 1.21V with 30mV hysteresis. In

Figure 4. VIN Undervoltage Lockout (UVLO)

Figure 5. VIN Overvoltage Lockout (OVLO)

LTM8083

GND

RUN/STOP

CONTROL

(OPTIONAL)

8083 F03

EN/UVLO

VIN

LTM8083

GND

8083 F04

OVLO

VIN

addition, the EN/UVLO pin sinks 2.5µA when the voltage

on the pin is below 1.21V. This current provides user

programmable hysteresis based on the value of R1. The

programmable UVLO thresholds are:

VIN(UVLO+) = 1.24V •

+ R2

+ 2.5µA • R1

VIN(UVLO–) = 1.21V •

+ R2

Figure 4 shows the implementation of external shutdown

control while still using the UVLO function. The NMOS

grounds the EN/UVLO pin when turned on, and puts the

LTM8083 in shutdown with 0.9µA quiescent current.

A resistor divider from VIN to the OVLO pin implements VIN

overvoltage lockout (OVLO). The OVLO rising threshold

is set at 1.235V with 115mV falling hysteresis. Figure 5

shows the implementation of VIN OVLO function. The pro-

grammable OVLO thresholds are:

VIN(OVLO+) = 1.235V •

+ R4

VIN(OVLO–) = 1.120V •

+ R4

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