AD4021 datasheet(20/39 Pages) AD

20 / 39 page

AD4020/AD4021/AD4022

Data Sheet

Rev. B | Page 20 of 39

APPLICATIONS INFORMATION

TYPICAL APPLICATION DIAGRAMS

Figure 40 shows an example of the recommended connection

diagram for the AD4020/AD4021/AD4022 when multiple

supplies, V+ and V−, are available. This configuration is used for

optimal performance because the amplifier supplies can be

selected to allow the maximum signal range (see Figure 40 for

the range).

Figure 41 shows a recommended connection diagram when

using a single-supply system. This setup is preferable when only

a limited number of rails are available in the system and power

dissipation is of critical importance.

Figure 42 shows a typical application diagram when using a

fully differential amplifier.

V+

REF

VDD

VIO

GND

IN+

IN–

SDI

SCK

SDO

CNV

AD4020/

AD4021/

AD4022

3-WIRE/4-WIRE

INTERFACE

1.8V

1.8V TO 5V

V+

≥ +6.5V

DIGITAL HOST

(MICROPROCESSOR/

FPGA)

V–

≤ –0.5V

HOST

SUPPLY

0.1µF

V–

V+

V–

AMP

VREF

VREF/2

REF

LDO

AMP

VREF/2

10µF

10kΩ

Figure 40. Typical Application Diagram with Multiple Supplies

REF

VDD

VIO

GND

IN+

IN–

SDI

SCK

SDO

CNV

AD4020/

AD4021/

AD40222

1.8V

1.8V TO 5V

V+ = +5V

DIGITAL HOST

(MICROPROCESSOR/

FPGA)

HOST

SUPPLY

0.1µF

100nF

4.096V

AMP

VREF

VREF/2

REF1

LDO

AMP

VREF/2

10µF2

10kΩ

1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.

2CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X7R).

3SEE THE DRIVER AMPLIFIER CHOICE SECTION.

4SEE THE ANALOG INPUTS SECTION.

3-WIRE/4-WIRE

INTERFACE

3, 4

Figure 41. Typical Application Diagram with a Single Supply

AD4021 датащи(PDF) 20 Page - Analog Devices

AD4021 датащи(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

датащи скачать

ссылки URL