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F1180 датащи(PDF) 9 Page - Integrated Device Technology |
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F1180 датащи(HTML) 9 Page - Integrated Device Technology |
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9 / 40 page ![]() Dual Path Lowband RF Receiver 400 MHz to 1100 MHz Glitch-Free TM, RF Receiver 9 Rev 1, April 2015 IDTF1130NBGI Datasheet PIN 8 LATCH ENABLE (LE): When LE is high (> VIH), the CLK input is disabled. IDT recommends keeping LE high to reduce F1130 sensitivity to CLK bus noise when SPI is not being programmed. When LE is low (< VIL), the DATA word can be programmed into the shift registers. The programmed word is then latched into F1130 on the LE rising edge (refer to Figure 1). End of data occurs after 14 th bit. DEFAULT REGISTER SETTING: After power on, the default setting for the VGA is Bypass OFF mode with attenuation set to 30 dB. This means the amplifier is in the signal path with maximum attenuation. TYPICAL OPERATING CONDITIONS (TOC) Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply. • VCC = +5.00 V • TCASE = +25 °C • FRF = 900 MHz • FIF = 199 MHz • FLO = 1100 MHz • PLO = 0 dBm • RF VGA output = -5 dBm/tone • RF Mixer output = 0 dBm/tone • Attenuator = 0 dB • STBY_A, STBY_B = GND |
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