ZSSC3240CC1B datasheet(13/64 Pages) RENESAS

13 / 64 page

ZSSC3240

Datasheet

Nov.27.20

Page 13

VTP

VTN

INP

INN

VSSB

Internal

Temp.

Sensor

Sensor Supply: Voltage / Ratiometric

Sensor Supply:

Current Mode

TEXT

Sensor

Bias

Current

VDDB

PGA

Gain_stage1

gain_polarity

ioffsc Gain_stage2

VDDAint

1.75V

adc_en_shift

adc_offset

adc_bits

Tbiasout

sensor_sup

Figure 4.

Analog Sensor Front-End Topology

6.2.1.

Programmable-Gain Amplifier (PGA)

The amplifier has a fully differential architecture and consists of two stages. The amplification of each stage and

the external sensor gain polarity are programmable via settings in the measurement configuration register:



For the main sensor element: SM_config1 and SM_config2 (NVM addresses 14HEX and 15HEX; see Table 34)



For an optional external temperature sensor: extTemp_config1 and extTemp_config2 (NVM addresses 16HEX

and 17HEX; see Table 34).

The first 7 bits of the *_config1 registers are the programmable gain settings Gain_stage1 and Gain_stage2. The

options for the programmable gain settings are listed in Table 5 and Table 6. The resulting analog gain is the

linear product of the stage 1 and stage 2 selection: GainPGA = Gain1

 Gain

. With the programmable

Gain_polarity bit in the *_config1 registers, the sign of the effective PGA gain can be swapped; e.g., to invert the

sensor characteristic’s slope and invert signal processing of the differential signal between INP and INN.

Table 5.

PGA Gain: Stage 1

Gain_stage1[3:0]

Gain1 [V/V]

bit[3]

bit[2]

bit[1]

bit[0]

1.2

120

150

200

240

300

Not assigned

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