5.2.3

Ground plane

Here are some recommendations with respect to the ground plane design:

•

Do not route any tracks to the right of the STM32WB5MMG and keep a large ground plane with the

associated ground via.

•

Route the tracks down directly on the top layer or with via to the other layers.

•

The ground plane must include the presence of vias (distance between two vias = 2 mm).

Ground via

Ground plane

Tracks

5.2.4

Sensitive GPIOs

This board contains three sensitive GPIOs as defined below:

•

PB10

•

PB11

•

PC5

The GPIO locations are illustrated in Figure 7

It is recommendedl to add a 3.3 pF capacitor in a small package (0201 or smaller) as close as possible to PB10,

PB11 and PC5 outputs of the STM32WB5MMG and also to border the GPIO tracks with ground.

Superposition of

four layers

Layer 1

Layer 4

Sensitive GPIO location on layer 1

Sensitive GPIO location on layer 4

5.2.5

Four layer reference board design

The reference schematics are illustrated in Figure 8 and the associated PCB layout is illustrated in Figure 9

By using the first external pad ring, the mother board on which the module is soldered may be designed with only

two layers. Using all the pads, the mother board must be designed with 4 layers.

STM32WB5MMG

Layout recommendations

DS13252 - Rev 1

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