STM32L021D4 datasheet(55/114 Pages) STMICROELECTRONICS

номер детали	STM32L021D4

подробное описание детали	Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AES

PDF	114 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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55 / 114 page

DocID027982 Rev 5

55/114

STM32L021x4

Electrical characteristics

Table 23. Current consumption in Run mode, code with data processing running from RAM

Symbol

Parameter

Conditions

fHCLK

Typ

Max(1)

Unit

IDD (Run

from

RAM)

Supply current in

Run mode, code

executed from

RAM, Flash

switched OFF

fHSE = fHCLK up to 16

MHz, included

fHSE = fHCLK/2 above

16 MHz

(PLL ON)(2)

Range 3,

VCORE=1.2 V,

VOS[1:0]=11

1 MHz

115

140

µA

2 MHz

205

240

4 MHz

385

420

Range 2,

VCORE=1.5 ,V,

VOS[1:0]=10

4 MHz

0.48

0.55

8 MHz

0.935

1.1

16 MHz

1.8

Range 1,

VCORE=1.8 V,

VOS[1:0]=01

8 MHz

1.1

1.4

16 MHz

2.1

2.5

32 MHz

4.5

4.9

MSI clock

Range 3,

VCORE=1.2 V,

VOS[1:0]=11

65 kHz

µA

524 kHz

4.2 MHz

415

450

HSI16 clock source

(16 MHz)

Range 2,

VCORE=1.5 V,

VOS[1:0]=10

16 MHz

1.95

2.2

Range 1,

VCORE=1.8 V,

VOS[1:0]=01

32 MHz

4.7

5.2

Guaranteed by characterization results

at 125 °C, not tested in production, unless otherwise specified.

Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

Table 24. Current consumption in Run mode vs code type,

code with data processing running from RAM(1)

Symbol

Parameter

Conditions

fHCLK

Typ

Unit

IDD (Run

from

RAM)

Supply current in

Run mode, code

executed from

RAM, Flash

switched OFF

fHSE = fHCLK up to 16

MHz, included,

fHSE = fHCLK/2 above

16 MHz (PLL ON)(2)

Range 3,

VCORE=1.2 V,

VOS[1:0]=11

Dhrystone

4 MHz

385

µA

CoreMark

-(3)

Fibonacci

350

while(1)

340

Range 1,

VCORE=1.8 V,

VOS[1:0]=01

Dhrystone

32 MHz

4.5

CoreMark

-(3)

Fibonacci

4.2

while(1)

Guaranteed by characterization results, not tested in production, unless otherwise specified.

Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

3. CoreMark code is unable to run from RAM since the RAM size is only 2 Kbytes.

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