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STM32F334C8U6TR датащи(PDF) 27 Page - STMicroelectronics |
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STM32F334C8U6TR датащи(HTML) 27 Page - STMicroelectronics |
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27 / 125 page ![]() DS9994 Rev 9 27/125 STM32F334x4 STM32F334x6 STM32F334x8 Functional overview 46 3.16 Communication interfaces 3.16.1 Inter-integrated circuit interface (I2C) The devices feature an I2C bus interface that can operate in multimaster and slave mode. It can support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz) modes. It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). It also includes programmable analog and digital noise filters. In addition, it provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. It also has a clock domain independent from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address match. The I2C interface can be served by the DMA controller. The features available in I2C1 are showed below in Table 7. Table 6. Comparison of I2C analog and digital filters - Analog filter Digital filter Pulse width of suppressed spikes ≥ 50 ns Programmable length from 1 to 15 I2C peripheral clocks Benefits Available in Stop mode 1. Extra filtering capability vs. standard requirements. 2. Stable length Drawbacks Variations depending on temperature, voltage, process Wakeup from Stop on address match is not available when digital filter is enabled. Table 7. STM32F334x4/6/8 I2C implementation I2C features(1) 1. X = supported. I2C1 7-bit addressing mode X 10-bit addressing mode X Standard mode (up to 100 kbit/s) X Fast mode (up to 400 kbit/s) X Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X Independent clock X SMBus X Wakeup from STOP X |
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