STM32F334C8U6TR datasheet(79/125 Pages) STMICROELECTRONICS

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DS9994 Rev 9

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STM32F334x4 STM32F334x6 STM32F334x8

Electrical characteristics

103

Output driving current

The GPIOs (general-purpose input/output) can sink or source up to +/-8 mA, and sink or

source up to +/- 20 mA (with a relaxed VOL/VOH).

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 6.2:

•

The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run

consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating

ΣIVDD (see Table 17).

•

The sum of the currents sunk by all the I/Os on VSS plus the maximum Run

consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating

ΣIVSS (see Table 17).

Output voltage levels

Unless otherwise specified, the parameters given in Table 47: ESD absolute maximum

ratings are derived from tests performed under ambient temperature and VDD supply

voltage conditions summarized in Table 19. All I/Os (FT, TTa and TC unless otherwise

specified) are CMOS and TTL compliant.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 24 and

Table 51. Output voltage characteristics

Symbol

Parameter

Conditions

Min.

Max.

Unit

VOL(1)

Low-level output voltage for an I/O pin

CMOS port(2)

IIO = +8 mA

2.7 V < VDD < 3.6 V

-0.4

VOH(3)

High- level output voltage for an I/O pin

VDD–0.4

VOL (1)

Low-level output voltage for an I/O pin

TTL port(2)

IIO = +8 mA

2.7 V < VDD < 3.6 V

-0.4

VOH (3)

High-level output voltage for an I/O pin

2.4

VOL(1)(4)

Low-level output voltage for an I/O pin

IIO = +20 mA

2.7 V < VDD < 3.6 V

-1.3

VOH(3)(4)

High-level output voltage for an I/O pin

VDD–1.3

VOL(1)(4)

Low-level output voltage for an I/O pin

IIO = +6 mA

2 V < VDD < 2.7 V

-0.4

VOH(3)(4)

High-level output voltage for an I/O pin

VDD–0.4

VOLFM+(1)(4)

Low-level output voltage for an FTf I/O pin

in FM+ mode

IIO = +20 mA

2.7 V < VDD < 3.6 V

-0.4

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 17 and the sum of

IIO (I/O ports and control pins) must not exceed ΣIIO(PIN).

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 17 and the sum

of IIO (I/O ports and control pins) must not exceed ΣIIO(PIN).

4. Data based on design simulation.

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