TAS5822MDCPR datasheet(51/90 Pages) TI

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7.6.1.16 DIG_VOL_CTRL1 Register (Offset = 4Eh) [reset = 0x33]

DIG_VOL_CTRL1 is shown in Figure 7-28 and described in Table 7-24.

Return to Table 7-7.

Figure 7-28. DIG_VOL_CTRL1 Register

PGA_RAMP_DOWN_SPEED

PGA_RAMP_DOWN_STEP

PGA_RAMP_UP_SPEED

PGA_RAMP_UP_STEP

R/W

Table 7-24. DIG_VOL_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

PGA_RAMP_DOWN_SPE

R/W

Digital Volume Normal Ramp Down Frequency

These bits control the frequency of the digital volume updates when

the volume is ramping down.

00: Update every 1 FS period

01: Update every 2 FS periods

10: Update every 4 FS periods

11: Directly set the volume to zero (Instant mute)

5-4

PGA_RAMP_DOWN_STE

R/W

Digital Volume Normal Ramp Down Step

These bits control the step of the digital volume updates when the

volume is ramping down.

00: Decrement by 4 dB for each update

01: Decrement by 2 dB for each update

10: Decrement by 1 dB for each update

11: Decrement by 0.5 dB for each update

3-2

PGA_RAMP_UP_SPEED R/W

Digital Volume Normal Ramp Up Frequency

These bits control the frequency of the digital volume updates when

the volume is ramping up.

00: Update every 1 FS period

01: Update every 2 FS periods

10: Update every 4 FS periods

11: Directly restore the volume (Instant unmute)

1-0

PGA_RAMP_UP_STEP

R/W

Digital Volume Normal Ramp Up Step

These bits control the step of the digital volume updates when the

volume is ramping up.

00: Increment by 4 dB for each updat

e 01: Increment by 2 dB for each update

10: Increment by 1 dB for each update

11: Increment by 0.5 dB for each update

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TAS5822M

SLASEV8 – DECEMBER 2020

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