VT6307L datasheet(32/54 Pages) VIA

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VT6307 PCI 1394a Host Controller

Revision 1.2 October 1, 2002

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Self-ID Control Registers

Memory Offset 64 – Self ID Buffer Pointer ................... RW

31-11 Self-ID Buffer Pointer................ default = undefined

Contains the base address of a 2K-byte buffer in host

memory where received Self-ID packets are stored.

10-0 Reserved

........................................ always reads 0

Memory Offset 68 – Self ID Count................................... RO

Self-ID Error .............................. default = undefined

Self-ID packet received with no errors (this bit

automatically

cleared

after

error-free

reception of a Self-ID packet)

Error detected during most recent Self-ID

packet reception (the contents of the Self-ID

Buffer are undefined in this case)

30-24 Reserved

........................................ always reads 0

23-16 Self-ID Generation ..................... default = undefined

The value in this field is incremented automatically

each time the Self-ID reception process begins. The

value rolls over after reaching 255.

15-13 Reserved

........................................ always reads 0

12-2 Self-ID Size ................................ default = undefined

Contains the length in 32-bit words of Self-ID data

that has been received. This field is cleared by 1394

bus reset.

1-0

Reserved

........................................ always reads 0

Channel Mask Registers

Offset 70 (Set), 74 (Clear) – Iso Rcv Channel Mask Hi . RW

31-0 Iso Channel Mask N+32 .....................default = 0000

Bits 31-0 correspond to channel numbers 63-32.

Writing 1 bits to offset 70 enables corresponding

channels for receiving isochronous data. Writing 1

bits to offset 74 disables corresponding channels from

receiving isochronous data.

Offset 78 (Set), 7C (Clear) – Iso Rcv Channel Mask Lo RW

31-0 Iso Channel Mask N+32 .....................default = 0000

Bits 31-0 correspond to channel numbers 31-0.

Writing 1 bits to offset 78 enables corresponding

channels for receiving isochronous data. Writing 1

bits to offset 7C disables corresponding channels

from receiving isochronous data.

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