VT6307 PCI 1394a Host Controller

Revision 1.2 October 1, 2002

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Table of Contents

Technologies, Inc.

We Connect

We Connect

We Connect

We Connect

FIGURE 1. CHIP INTERNAL BLOCK DIAGRAM.....................................................................................................................3

FIGURE 2. INTERNAL PHY BLOCK DIAGRAM ......................................................................................................................4

FIGURE 3. VT6307 1394A CONTROLLER PQFP - 128 PIN DIAGRAM 14X20 (TOP VIEW) .............................................5

FIGURE 4. VT6307L 1394A CONTROLLER LQFP - 128 PIN DIAGRAM 14X20 (TOP VIEW) ..........................................6

FIGURE 5. VT6307S 1394A CONTROLLER LQFP - 128 PIN DIAGRAM 14X14 (TOP VIEW)...........................................7

FIGURE 6. CABLE INTERFACE.................................................................................................................................................40

FIGURE 7. MECHANICAL SPECIFICATIONS – VT6307 RECTANGULAR 128-PIN PQFP PACKAGE .......................46

FIGURE 8. MECHANICAL SPECIFICATIONS - VT6307L RECTANGULAR 128-PIN LQFP PACKAGE .....................47

FIGURE 9. MECHANICAL SPECIFICATIONS - VT6307S SQUARE 128-PIN LQFP PACKAGE ....................................48

TABLE 1. PIN LIST – VT6307/VT6307L (ALPHABETICAL ORDER) ....................................................................................8

TABLE 2. PIN LIST – VT6307S (ALPHABETICAL ORDER) ...................................................................................................9

TABLE 3. PIN DESCRIPTIONS ...................................................................................................................................................10

TABLE 4. REGISTERS..................................................................................................................................................................15

TABLE 5. PHY REGISTER MAP.................................................................................................................................................18

TABLE 6. PACKET EVENT CODES...........................................................................................................................................33

TABLE 7. PHY REGISTER PAGE 0 BIT FIELD DESCRIPTIONS ........................................................................................38

TABLE 8. PHY REGISTER PAGE 1 BIT FIELD DESCRIPTIONS ........................................................................................38