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VT6307 датащи(PDF) 44 Page - VIA Technologies, Inc.

номер детали VT6307
подробное описание детали  PCI 1394a-2000 Integrated Host Controller
PDF  54 Pages
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производитель  VIA [VIA Technologies, Inc.]
домашняя страница  https://www.viatech.com/en/
Logo VIA - VIA Technologies, Inc.

VT6307 датащи(HTML) 44 Page - VIA Technologies, Inc.

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VT6307 PCI 1394a Host Controller
Revision 1.2 October 1, 2002
-38-
Register Descriptions
Technologies, Inc.
We Connect
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PHY Register Page 0 - Port Status
The Port Status page is used to access configuration and status
information for each of the PHY’s port. The port is selected by
writing zero to Page_select and the desired port number to
Port_select in the PHY register at address 0111.
Offset
7
6
5
4
3
2
1
0
1000b Disa
Bias Conn Child
Bstat
Astat
1001b
-reserved-
Fault IntEn
Negotiated Speed
1010b
-reserved-
1011b
-reserved-
1100b
-reserved-
1101b
-reserved-
1110b
-reserved-
1111b
-reserved-
Table 7. PHY Register Page 0 Bit Field Descriptions
Field
Bits Type Def Description
Astat
2
R
-
TPA line state for the port
00 = invalid
01 =1
10 =0
11 =z
Bstat
2
R
-
Same encoding as Astat
Child
1
R
-
1 indicates the port is a child, 0 a parent.
The meaning of this bit is undefined
from the time a bus reset is detected until
the chip transitions to state T1:Child
Handshake
during
the
tree
identify
process (see 4.4.2.2 in IEEE 1394-1995)
Conncted
1
R
0
One indicates the port is connected, zero
indicates it is disconnected. The value
reported by this bit is filtered by
hysteresis logic to reduce multiple status
changes caused by contact scrape when a
connector is inserted or removed.
Bias
1
R
-
One
indicates
that
bias
voltage
is
detected (possible connection).
The
value reported by this bit is filtered by
hysteresis logic to reduce multiple status
changes caused by contact scrape when a
connector is inserted or removed.
Disabled
1
RW
0
When set to one, the port is disabled. The
value of this bit subsequent to a power
reset is implementation-dependent, but
should be a strappable option.
Negotiated
Speed
3
R
-
Indicates the maximum speed negotiated
between this port and its immediately
connected port.
000 – 98.304 Mbit/s
001 - and 196.608 Mbit/s
010 - and 393.216 Mbit/s
Interrupt
Enable
1
RW
0
Enable port event interrupts. When set
to one, the chip sets Port_event to one if
any of Connected, Bias, Disabled or
Fault (for this port) change state.
Fault
1
rw
0
Set to one if an error is detected during a
suspend or resume operation. A write of
one to this bit clears it to zero.
PHY Register Page 1 - Vendor Identification
The Vendor Identification page is used to identify the
VT6307’s vendor and compliance level. The page is selected
by writing one to Page_select in the PHY register at address
0111.
Offset
7654
3
2
1
0
1000b
Compliance Level
1001b
-reserved-
1010b
1011b
1100b
Vendor ID
1101b
1110b
1111b
Product ID
Table 8. PHY Register Page 1 Bit Field Descriptions
Field
Bits Type Default Description
Compliance
Level
8
R
1
“1” indicates IEEE P1394a
Vendor ID
24
R
00 40 63 The
company
ID
or
Organizationally
Unique
Identifier
(OUI)
of
the
manufacturer of the PHY. The
most
significant
byte
of
Vendor_ID
appears
at
PHY
register location 1010 and the
least significant at 1100.
Product ID
24
R
30 60 00 The meaning of this number is
determined by the company or
organization
that
has
been
granted Vendor_ID.
The most
significant byte of Product_ID
appears at PHY register location
1101 and the least significant at
1111.



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