SN74LS174D datasheet(4/8 Pages) ONSEMI

4 / 8 page

SN74LS174

http://onsemi.com

AC CHARACTERISTICS (TA = 25°C)

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

fMAX

Maximum Input Clock Frequency

MHz

tPHL

Propagation Delay, MR to Output

VCC = 5.0 V

15 F

tPLH

tPHL

Propagation Delay, Clock to Output

CL = 15 pF

AC SETUP REQUIREMENTS (TA = 25°C)

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Clock or MR Pulse Width

Data Setup Time

VCC =5 0V

Data Hold Time

5.0

VCC = 5.0 V

trec

Recovery Time

AC WAVEFORMS

Figure 1. Clock to Output Delays, Clock Pulse Width,

Frequency, Setup and Hold Times Data to Clock

Figure 2. Master Reset to Output Delay, Master Reset

Pulse Width, and Master Reset Recovery Time

*The shaded areas indicate when the input is permitted to

*change for predictable output performance.

1.3 V

1/fmax

ts(H)

th(H)

ts(L)

th(L)

tPHL

tPLH

tPHL

trec

1.3 V

DEFINITIONS OF TERMS

SETUP TIME (ts) — is defined as the minimum time

required for the correct logic level to be present at the logic

input prior to the clock transition from LOW to HIGH in

order to be recognized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time

following the clock transition from LOW to HIGH that the

logic level must be maintained at the input in order to ensure

continued recognition. A negative HOLD TIME indicates

that the correct logic level may be released prior to the clock

transition from LOW to HIGH and still be recognized.

RECOVERY TIME (trec) — is defined as the minimum time

required between the end of the reset pulse and the clock

transition from LOW to HIGH in order to recognize and

transfer HIGH Data to the Q outputs.

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