SN74LS174

http://onsemi.com

3

FUNCTIONAL DESCRIPTION

The LS174 consists of six edge-triggered D flip-flops with

individual D inputs and Q outputs. The Clock (CP) and

Master Reset (MR) are common to all flip-flops.

Each D input’s state is transferred to the corresponding

flip-flop’s output following the LOW to HIGH Clock (CP)

transition.

A LOW input to the Master Reset (MR) will force all

outputs LOW independent of Clock or Data inputs. The

LS174 is useful for applications where the true output only

is required and the Clock and Master Reset are common to

all storage elements.

TRUTH TABLE

Inputs (t = n, MR = H)

Outputs (t = n+1) Note 1

D

Q

H

H

L

L

Note 1: t = n + 1 indicates conditions after next clock.

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage for

All Inputs

Input Clamp Diode Voltage

– 0.65

– 1.5

V

Output HIGH Voltage

2.7

3.5

V

Output LOW Voltage

0.25

0.4

V

Output LOW Voltage

0.35

0.5

V

per Truth Table

I

Input HIGH Current

20

µA

Input HIGH Current

0.1

mA

Input LOW Current

– 0.4

mA

Short Circuit Current (Note 1)

–20

– 100

mA

Power Supply Current

26

mA

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.