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Data Sheet

AD9166

Rev. 0 | Page 29 of 138

JESD204B SERIAL DATA INTERFACE

JESD204B OVERVIEW

The AD9166 has eight JESD204B data ports that receive data.

The eight JESD204B ports can be configured as part of a single

JESD204B link that uses a single system reference (SYSREF±) and

device clock (CLK±).

The JESD204B serial interface hardware consists of three layers:

the physical layer, the data link layer, and the transport layer.

These sections of the hardware are described in subsequent

sections, including information for configuring every aspect of

the interface. Figure 48 shows the communication layers

implemented in the AD9166 serial data interface to recover the

clock and deserialize, descramble, and deframe the data before it

is sent to the digital signal processing section of the device.

The physical layer establishes a reliable channel between the

transmitter and the receiver, the data link layer is responsible

for unpacking the data into octets and descrambling the data.

The transport layer receives the descrambled JESD204B frames

and converts them to DAC samples.

Various JESD204B parameters (L, F, K, M, N, NP, S, HD) define

how the data is packed and tell the device how to turn the serial

data into samples. These parameters are defined in the Transport

Layer section. The AD9166 also has a descrambling option (see

the Descrambler section for more information).

The various combinations of JESD204B parameters that are

supported depend solely on the number of lanes. Thus, a

unique set of parameters can be determined by selecting the

lane count to be used. In addition, the interpolation rate and

number of lanes can be used to define the rest of the configura-

tion needed to set up the AD9166. The interpolation rate and

the number of lanes are selected in Register 0x110.

The AD9166 has a single DAC output. However, for the

purposes of the complex signal processing on chip, whenever

interpolation is used, the converter count is defined as M = 2.

For a particular application, the number of converters to use

(M) and the data rate variable (DataRate) are known. The lane

rate variable (LaneRate) and number of lanes (L) can be traded

off as follows:

DataRate = (DACRate)/(InterpolationFactor)

LaneRate = (20 × DataRate × M)/L

where LaneRate must be between 750 Mbps and 12.5 Gbps.

Achieving and recovering synchronization of the lanes is very

important. To simplify the interface to the transmitter, the

AD9166 designates a master synchronization signal for each

JESD204B link. The SYNCOUT− and SYNCOUT+ pins are used

as the master signal for all lanes. If any lane in a link loses

synchronization, a resynchronization request is sent to the

transmitter via the synchronization signal of the link. The

transmitter stops sending data and instead sends synchronization

characters to all lanes in that link until resynchronization is

achieved.

DESERIALIZER

DATA LINK

LAYER

TRANSPORT

LAYER

SERDIN0±

SYSREF±

SERDIN7±

I DATA[15:0]

Q DATA[15:0]

TO DAC

DSP BLOCK

SYNCOUT+/SYNCOUT–

PHYSICAL

LAYER

DESERIALIZER

QBD/

DESCRAMBLER

FRAME TO

SAMPLES

Figure 48. Functional Block Diagram of Serial Link Receiver

Table 15. Single-Link JESD204B Operating Modes

Number of Lanes (L)

Parameter

Parametric Symbol

Lane Count

Converter Count

1 (real), 2 (complex)

Octets per Frame per Lane

Samples per Converter per Frame

4 (real), 2 (complex)

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