AD9166 datasheet(32/138 Pages) AD

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AD9166

Data Sheet

Rev. 0 | Page 32 of 138

SERDES PLL

Functional Overview of the SERDES PLL

The independent SERDES phase-locked loop (PLL) uses

Integer N techniques to achieve clock synthesis. The entire

SERDES PLL is integrated on chip, including the voltage

controlled oscillator (VCO) and the loop filter. The SERDES

PLL VCO operates over the range of 6 GHz to 12.5 GHz.

In the SERDES PLL, a VCO divider block divides the VCO

clock by 2 to generate a 3 GHz to 6.25 GHz quadrature clock for

the deserializer cores. This clock is the input to the CDR block

that is described in the Clock and Data Recovery section.

The reference clock to the SERDES PLL is always running at a

frequency, fREF, that is equal to 1/40 of the lane rate (PCLK rate).

The fREF frequency is divided by an integer factor, set by SERDES_

PLL_DIV_FACTOR, to deliver a clock to the phase frequency

detector (PFD) block, fPFD, that is between 35 MHz and 80 MHz.

Table 18 includes the respective SERDES_PLL_DIV_FACTOR

options available.

Table 18. SERDES PLL Divider Settings

Lane Rate

(Gbps)

PLL_REF_CLK_RATE

(Register 0x084,

Bits[5:4])

SERDES_PLL_DIV_FACTOR

(Register 0x289, Bits[1:0])

0.750 to 1.5625

0b01 = 2×

0b10 = ÷1

1.5 to 3.125

0b00 = 1×

0b10 = ÷1

3 to 6.25

0b00 = 1×

0b01 = ÷2

6 to 12.5

0b00 = 1×

0b00 = ÷4

SERDES PLL Enable and Recalibration

To enable the SERDES PLL, first set the PLL divider register

(see Table 18). Then enable the SERDES PLL by writing

rising edge of the bit causes a recalibration to begin.

Confirm that the SERDES PLL is working by reading

has locked. If Register 0x281, Bit 3 = 1, the SERDES PLL

calibration has completed. If Register 0x281, Bit 4 or Bit 5 is

high, the PLL reaches the lower or upper end of its calibration

band and must be recalibrated by writing 0 and then 1 to

Clock and Data Recovery (CDR)

The deserializer is equipped with a CDR circuit. Instead of

recovering the clock directly from the JESD204B serial lanes, the

CDR circuit continuously aligns the phase of the sampling

clocks for each SERDES lane with the incoming bit stream from

the JESD204B transmitter. The sampling clocks are derived

from the SERDES PLL. The 3 GHz to 6.25 GHz sampling clocks

are derived from the SERDES PLL, as shown in Figure 54, at the

input to the CDR.

To generate the lane rate clock inside the device, a CDR

sampling mode must be selected as follows:



For a lane rate greater than 6.25 Gbps, use half rate CDR.



For a lane rate between 3 Gbps and 6.25 Gbps, disable half

rate operation.



For a lane rate less than 3 Gbps, disable full rate and enable

2× oversampling to recover the appropriate lane rate clock.

Table 19 lists the CDR sampling settings that must be set

depending on the lane rate value.

Table 19. CDR Operating Modes

Lane Rate

(Gbps)

SPI_ENHALFRATE

(Register 0x230,

Bit 5)

SPI_DIVISION_RATE

(Register 0x230,

Bits[2:1])

0.750 to 1.5625

0 (full rate)

0b10 (divide by 4)

1.5 to 3.125

0 (full rate)

0b01 (divide by 2)

3 to 6.25

0 (full rate)

0b00 (no divide)

6 to 12.5

1 (half rate)

0b00 (no divide)

The CDR circuit synchronizes the phase used to sample the data on

each serial lane independently. This independent phase adjustment

per serial interface ensures accurate data sampling and eases the

implementation of multiple serial interfaces on a PCB.

After configuring the CDR circuit, reset it and then release the

reset by writing 0 and then writing 1 to Register 0x206, Bit 0.

In some clocking configuration, it may be necessary to reset the

CDR after the JESD204B transmitter begins sending /K/

characters as part of the JESD204B serial link establishment, so

that the CDR restarts its search loop and aligns the clocks

correctly (see the JESD204B Serial Link Establishment section).

Power-Down Unused PHYs

Unused lanes that are left enabled consume extra power

unnecessarily. Each lane that is not in use (SERDINx±) must be

powered off by writing a 1 to the corresponding bit of PHY_PD

(Register 0x201).

Equalization

To compensate for signal integrity distortions for each PHY

channel due to PCB trace length and impedance, the AD9166

employs an easy to use, low power equalizer on each JESD204B

channel. The AD9166 equalizers can compensate for insertion

losses far greater than required by the JESD204B specification.

The equalizers have two modes of operation that are determined

by the EQ_POWER_MODE register setting in Register 0x268,

Bits[7:6]. In low power mode (Register 0x268, Bits[7:6] = 0b01)

and operating at the maximum lane rate of 12.5 Gbps, the

equalizer can compensate for up to 11.5 dB of insertion loss. In

normal mode (Register 0x268, Bits[7:6] = 0b00), the equalizer

can compensate for up to 17.2 dB of insertion loss. This perfor-

mance is shown in Figure 51 as an overlay to the JESD204B

specification for insertion loss. Figure 51 shows the equalization

performance at 12.5 Gbps, near the maximum baud rate for the

AD9166.

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