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MGC3140 датащи(PDF) 23 Page - Microchip Technology |
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MGC3140 датащи(HTML) 23 Page - Microchip Technology |
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23 / 49 page ![]() Figure 6-4. Brown-out Reset Timing MCLR BOR TMCLR TBOR Reset Sequence CPU Starts Fetching Code (TSYSDLY BOR voltage = 2.25V to 2.45V ) 6.2 Power Management Unit (PMU) 6.2.1 Basic Connection Requirements The device requires a nominal 3.3V supply voltage. The following pins need to be connected: • All VDD and VSS pins need connection to the supply voltage and decoupling capacitors • VCORECAP: The devices’ core and digital logic is designed to operate at a nominal 1.8V, which is provided by an on-chip regulator. The required core logic voltage is derived from VDD and is outputted on the VCORECAP pin. A low-ESR capacitor (such as tantalum) must be connected to the VCORECAP pin. This helps to maintain the stability of the regulator. • AVDD: Analog voltage references for the ADC needs to be connected to the supply voltage and a decoupling capacitor • VANA: Analog supply for GestIC analog front end must be connected to the supply voltage Figure 6-5. Connections for VCORE Regulator VDD VCORECAP VSS CEFC (2,3 ) 3.3V (1) (10 uF typ) Note: MGC3140 Functional Description © 2018 Microchip Technology Inc. DS40002037A-page 23 |
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