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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MGC3140 датащи(PDF) 22 Page - Microchip Technology |
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MGC3140 датащи(HTML) 22 Page - Microchip Technology |
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22 / 49 page  A simplified block diagram of the Reset block is illustrated in the following figure. A pull-up resistor of 10 kΩ must be connected at all times to the MCLR pin. Figure 6-2. System Reset Block Diagram PIC16(L)F18325/18345 DS40000000A-page 74 Preliminary 2017 Microchip Technology Inc. FIGURE 5-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT MCLR VDD Brown-out Reset Glitch Filter MCLR Deep Sleep WDT Time-out POR WDTR BOR Power-up Timer VDD Rise Detect Voltage Regulator Enabled Software Reset SWR SYSRST Timing Diagrams for POR and BOR are shown below: Figure 6-3. Power-on Reset Timing VDD VPOR Power-up Sequence (Note 2) (TPU) CPU Starts Fetching Code (Note 1) (TSYSDLY) Note: 1. The power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN). 2. Includes interval voltage regulator stabilization delay. MGC3140 Functional Description © 2018 Microchip Technology Inc. DS40002037A-page 22 |
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