USB334X datasheet(29/92 Pages) MICROCHIP

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DS00002646A-page 29

USB334x

5.5.1.2

ULPI Clock Output Mode

When using ULPI Clock Output Mode, the USB334x generates the 60 MHz ULPI clock used by the Link. In this mode,

the REFCLK pin must be driven with the model-specific frequency, and the CLKOUT pin sources the 60 MHz ULPI

clock to the Link. When using ULPI Clock Output Mode, the system must not drive the CLKOUT pin following POR or

hardware reset with a voltage that exceeds the value of VIH_ED provided in Table 4-4. An example of ULPI Clock Output

Mode is shown in Figure 8-1

After the PLL has locked to the correct frequency, the USB334x generates the 60 MHz ULPI clock on the CLKOUT pin,

and de-asserts DIR to indicate that the PLL is locked. The USB334x will start the clock within the time specified in

Table 4-3, and it will be accurate to within ±500ppm. For Host applications the ULPI AutoResume bit should be enabled.

This is described in Section 6.4.1.4, "Host Resume K," on page 53.

When using ULPI Clock Output Mode, the edges of the reference clock do not need to be aligned in any way to the ULPI

interface signals. There is no need to align the phase of the REFCLK and the CLKOUT.

For the USB3341, USB3343, USB3346, and USB3347, the reference clock frequency required is shown in the Product

Identification System section.

5.5.2

REFCLK AMPLITUDE

The reference clock should be connected to the REFCLK pin as shown in the application diagrams, . The REFCLK pin

is designed to be driven with a square wave from 0V to VDD18 (USB3341, USB3346, and USB3347) or VDDIO

(USB3343), but can be driven with a square wave from 0V to as high as 3.6V. The USB334x uses only the positive edge

of the REFCLK.

If a digital reference is not available, the REFCLK pin can be driven by an analog sine wave that is AC coupled into the

REFCLK pin. If using an analog clock the DC bias should be set at the mid-point of the VDD18 supply using a bias

circuit as shown in Figure 5-5. The amplitude must be greater than 300mV peak to peak. The component values pro-

vided in Figure 5-5 are for example only. The actual values should be selected to satisfy system requirements.

The REFCLK amplitude must comply with the signal amplitudes shown in Table 4-5 and the duty cycle in Table 4-3.

FIGURE 5-4:

CONFIGURING THE USB334X FOR ULPI CLOCK OUTPUT MODE

CLKOUT

REFCLK

MCHP PHY

From PLL

Clock

Source

To PLL

Link

ULPI Clk In

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