SST26VF064BEUI datasheet(4/81 Pages) MICROCHIP

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 2015-2018 Microchip Technology Inc.

DS20006138A-page 4

SST26VF064BEUI

2.0

PIN DESCRIPTION

FIGURE 2-1:

PIN DESCRIPTION FOR 8-LEAD SOIJ

FIGURE 2-2:

PIN DESCRIPTION FOR 8-CONTACT WDFN

TABLE 2-1:

PIN DESCRIPTION

Symbol

Pin Name

Functions

SCK

Serial Clock

To provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the clock

input, while output data is shifted out on the falling edge of the clock input.

SIO[3:0]

Serial Data

Input/Output

To transfer commands, addresses, or data serially into the device or data out of

the device. Inputs are latched on the rising edge of the serial clock. Data is

shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)

command instruction configures these pins for Quad I/O mode.

Serial Data Input

for SPI mode

To transfer commands, addresses or data serially into the device. Inputs are

latched on the rising edge of the serial clock. SI is the default state after a power

on reset.

Serial Data Output

for SPI mode

To transfer data serially out of the device. Data is shifted out on the falling edge

of the serial clock. SO is the default state after a power on reset.

CE#

Chip Enable

The device is enabled by a high to low transition on CE#. CE# must remain low

for the duration of any command sequence; or in the case of Write operations,

for the command/data input sequence.

WP#

Write Protect

The WP# is used in conjunction with the WPEN and IOC bits in the Configura-

tion register to prohibit write operations to the Block-Protection register. This pin

only works in SPI, single-bit and dual-bit Read mode.

CE#

SO/SIO1

WP#/SIO2

VSS

VDD

HOLD/SIO3

SCK

SI/SIO0

Top View

25119 08-soic S2A P1.0

CE#

SO/SIO1

WP#/SIO2

VSS

Top View

VDD

HOLD/SIO3

SCK

SI/SIO0

25119 08-wson QA P1.0

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