PFS173 datasheet(68/105 Pages) PADAUK

68 / 105 page

PFS173

8bit MTP MCU with 8-bit ADC

Page 68 of 105

PDK-DS-PFS173-EN_V105-Jun. 19, 2020

6.4. Interrupt Enable Register (inten), IO address = 0x04

Bit

Reset

R/W

Description

R/W

Enable interrupt from Timer3. 0 / 1: disable / enable

R/W

Enable interrupt from Timer2. 0 / 1: disable / enable

R/W

Enable interrupt from PWMG. 0 / 1: disable / enable

R/W

Enable interrupt from comparator. 0 / 1: disable / enable

R/W

Enable interrupt from ADC. 0 / 1: disable / enable

R/W

Enable interrupt from Timer16 overflow. 0 / 1: disable / enable

R/W

Enable interrupt from PB0/PA4. 0 / 1: disable / enable

R/W

Enable interrupt from PA0/PB5. 0 / 1: disable / enable

6.5. Interrupt Request Register (intrq), IO address = 0x05

Bit

Reset

R/W

Description

R/W

Interrupt Request from Timer3, this bit is set by hardware and cleared by software.

0 / 1: No request / Request

R/W

Interrupt Request from Timer2, this bit is set by hardware and cleared by software.

0 / 1: No request / Request

R/W

Interrupt Request from PWMG, this bit is set by hardware and cleared by software.

0 / 1: No request / Request

R/W

Interrupt Request from comparator, this bit is set by hardware and cleared by software.

0 / 1: No request / Request

R/W

Interrupt Request from ADC, this bit is set by hardware and cleared by software.

0 / 1: No request / Request

R/W

Interrupt Request from Timer16, this bit is set by hardware and cleared by software.

0 / 1: No request / Request

R/W

Interrupt Request from pin PB0/PA4, this bit is set by hardware and cleared by software.

0 / 1: No request / Request

R/W

Interrupt Request from pin PA0/PB5, this bit is set by hardware and cleared by software.

0 / 1: No Request / request

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