DF69 datasheet(73/106 Pages) PADAUK

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DF69

DC Fan Controller

6-25. ADC Result High Register (adcrh), IO address = 0x22

Bit

Reset

R/W

Description

7 – 0

These eight read-only bits will be the bit [9:2] of AD conversion result. The bit 7 of this

6-26. ADC Result Low Register (adcrl), IO address = 0x23

Bit

Reset

R/W

Description

7 – 6

These two bits will be the bit [1:0] of AD conversion result.

5 – 0

Reserved

6-27. Timer2 Control Register (tm2c), IO address = 0x3c

Bit

Reset

R/W

Description

7 – 4

0000

R/W

Timer2 clock selection.

0000 : disable

0001 : system clock

0010 : internal high RC oscillator (IHRC)

0011 : reserved

0100 : ILRC

0101 : reserved

011x : reserved

1000 : PA0 (rising edge)

1001 : ~PA0 (falling edge)

1010 : PB0 (rising edge)

1011 : ~PB0 (falling edge)

1100 : PA4 (rising edge)

1101 : ~PA4 (falling edge)

Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2

does NOT be stopped, Timer2 will keep counting when ICE is in halt state.

3 – 0

Reserved, please keep 0.

6-28. Timer2 Counter Register (tm2ct), IO address = 0x3d

Bit

Reset

R/W

Description

7 – 0

0x00

R/W

Bit [7:0] of Timer2 counter register.

Page 73 of 106

PDK-DS-DF69_V003 – Apr. 18, 2018

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