MPC5673K datasheet(13/147 Pages) NXP

13 / 147 page

Introduction

MPC5675K Microcontroller Data Sheet, Rev. 8.1

NXP Semiconductors

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PWM outputs can operate as complementary pairs or independent channels

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Ability to accept signed numbers for PWM generation

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Independent control of both edges of each PWM output

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Synchronization to external hardware or other PWM is supported

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Double-buffered PWM registers

— Integral reload rates from 1 to 16

— Half-cycle reload capability

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Multiple ADC trigger events can be generated per PWM cycle via hardware

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Fault inputs can be assigned to control multiple PWM outputs

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Programmable filters for fault inputs

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Independently programmable PWM output polarity

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Independent top and bottom deadtime insertion

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Each complementary pair can operate with its own PWM frequency and deadtime values

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Individual software control for each PWM output

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All outputs can be forced to a value simultaneously

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PWMX pin can optionally output a third signal from each channel

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Channels not used for PWM generation can be used for:

— buffered output compare functions

— input capture functions

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Enhanced dual-edge capture functionality

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Option to supply the source for each complementary PWM signal pair from any of the following:

— External digital pin

— Internal timer channel

— External ADC input, taking into account values set in ADC high and low limit registers

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Supports safety measures using DMA

1.6.20.2

Cross Triggering Unit (CTU)

The CTU provides automatic generation of ADC conversion requests on user-selected conditions without CPU load during the

PWM period and with minimized CPU load for dynamic configuration.

The CTU implements the following features:

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Cross triggering between ADC, FlexPWM, eTimer, and external pins

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Double-buffered trigger generation unit with as many as eight independent triggers generated from external triggers

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Maximum operating frequency lower than or equal to platform

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Trigger generation unit configurable in sequential mode or in triggered mode

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Trigger delay unit to compensate the delay of external low-pass filter

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Double-buffered global trigger unit allowing eTimer synchronization and/or ADC command generation

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Double-buffered ADC command list pointers to minimize ADC trigger unit update

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Double-buffered ADC conversion command list with as many as twenty-four ADC commands

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Each trigger has the capability to generate consecutive commands

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ADC conversion command allows controlling ADC channel from each ADC, single or synchronous sampling,

independent result queue selection

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Supports safety measures using DMA

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