MPC5673K datasheet(16/147 Pages) NXP

16 / 147 page

MPC5675K Microcontroller Data Sheet, Rev. 8.1

Introduction

NXP Semiconductors

1.6.26

Non-Maskable Interrupt (NMI)

The non-maskable interrupt with de-glitching filter is available to support high priority core exceptions.

1.6.27

System Status and Configuration Module (SSCM)

The SSCM on the MPC5675K features the following:

•

System configuration and status

•

Debug port status and debug port enable

•

Multiple boot code starting locations out of reset through implementation of search for valid reset configuration

halfword

•

Sets up the MMU to allow user boot code to execute as either Classic Power Architecture Book E code (default) or as

NXP VLE code out of flash

•

Supports serial bootloading of either Classic Power Architecture Book E code (default) or NXP VLE code

•

Detection of user boot code

•

Automatic switch to serial boot mode if internal flash is blank or invalid

1.6.28

Nexus Development Interface (NDI)

•

Per IEEE-ISTO 5001-2008

•

Real-time development support for Power Architecture core through Nexus class 3 (some class 4 support)

•

Nexus support to snoop system SRAM traffic

•

Data trace of FlexRay accesses

•

Read and write access

•

Configured via the IEEE 1149.1 (JTAG) port

•

High bandwidth mode for fast message transmission

•

Reduced bandwidth mode for reduced pin usage

1.6.29

IEEE 1149.1 JTAG Controller (JTAGC)

•

IEEE 1149.1-2001 Test Access Port (TAP) interface

•

JCOMP input that provides the ability to share the TAP —selectable modes of operation include JTAGC/debug or

normal system operation

•

5-bit instruction register that supports IEEE 1149.1-2001 defined instructions

•

5-bit instruction register that supports additional public instructions

•

Three test data registers:

— Bypass register

— Boundary scan register

— Device identification register

•

TAP controller state machine that controls the operation of the data registers, instruction register, and associated

circuitry

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