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ASM5P2304B датащи(PDF) 7 Page - Alliance Semiconductor Corporation

номер детали ASM5P2304B
подробное описание детали  3.3V Zero Delay Buffer
PDF  13 Pages
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производитель  ALSC [Alliance Semiconductor Corporation]
домашняя страница  https://www.alliancememory.com
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September 2005
ASM5P2304B
rev 0.5
3.3V Zero Delay Buffer
7 of 13
Notice: The information in this document is subject to change without notice.
Switching Characteristics for ASM5I2304B Industrial Temperature Devices
All parameters are specified with loaded outputs
Parameter
Description
Test Conditions
Min Typ Max Unit
t1
Output Frequency
30pF load,-1, -1H,-2, -2H devices
4
20 MHz
Duty Cycle
8 = (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = <20MHz
30pF load
40.0 50.0 60.0
%
Duty Cycle
8= (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = <20MHz
15pF load
45.0 50.0 55.0
%
t3
Output Rise Time
8
(-1, -2)
Measured between 0.8V and 2.0V
30pF load
2.50 nS
t3
Output Rise Time
8
(-1, -2)
Measured between 0.8V and 2.0V
15pF load
1.50 nS
t3
Output Rise Time
8
(-1H, -2H)
Measured between 0.8V and 2.0V
30pF load
1.50 nS
t4
Output Fall Time
8
(-1, -2)
Measured between 2.0V and 0.8V
30pF load
2.50 nS
t4
Output Fall Time
8
(-1, -2)
Measured between 2.0V and 0.8V
15pF load
1.50 nS
t4
Output Fall Time
8
(-1H, -2H)
Measured between 2.0V and 0.8V
30pF load
1.25
ns
Output-to-output skew on same bank
(-1, -2)
8
All outputs equally loaded
200
Output-to-output skew
(-1H, -2H)
All outputs equally loaded
200
Output bank A -to- output bank B skew
(-1, -2H)
All outputs equally loaded
200
t5
Output bank A -to- output bank B skew
(-2)
All outputs equally loaded
400
pS
t6
Delay, REF Rising Edge to FBK Rising
Edge
8
Measured at VDD /2
0
±250 pS
t7
Device-to-Device Skew
8
Measured at VDD/2 on the FBK pins of the
device
0
500
pS
t8
Output Slew Rate
8
Measured between 0.8V and 2.0V using
Test Circuit #2
1
V/nS
Measured at 20MHz, loaded outputs,
15pF load
180
Measured at 20MHz, loaded outputs,
30pF load
200
tJ
Cycle-to-cycle jitter
8
(-1, -1H, -2H)
Measured at 20MHz, loaded outputs,
15pF load
100
pS
Measured at 20MHz, loaded outputs,
30pF load
400
tJ
Cycle-to-cycle jitter
8
(-2)
Measured at 20MHz, loaded outputs,
15pF load
380
pS
tLOCK
PLL Lock Time
8
Stable power supply, valid clock presented
on REF and FBK pins
1.0
mS
Note:
8. Parameter is guaranteed by design and characterization. Not 100% tested in production
.



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