September 2005

ASM5P2304B

rev 0.5

3.3V Zero Delay Buffer

3 of 13

Notice: The information in this document is subject to change without notice.

CLKB1

1

2

3

4

5

6

7

8

ASM5P2304B

REF

CLKA1

CLKA2

GND

CLKB2

FBK

Pin Configuration

Pin Description for ASM5P2304B

Pin #

Pin Name

Description

1

REF

1

Input reference frequency, 5V tolerant input

2

CLKA1

2

Buffered clock output, bank A

3

CLKA2

2

Buffered clock output, bank A

4

GND

Ground

5

CLKB1

2

Buffered clock output, bank B

6

CLKB2

2

Buffered clock output, bank B

7

3.3V supply

8

FBK

PLL feedback input

Notes:

1. Weak pull-down.

2. Weak pull-down on all outputs.