NFAQ0860L36T

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8

APPLICATIONS INFORMATION

Input / Output Timing Chart

Figure 12. Input / Output Timing Chart

NOTES:

1. This section of the timing diagram shows the effect of cross−conduction prevention.

2. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go

low, switching off all six IGBTs. When the voltage on VDD rises sufficiently, normal operation will resume.

3. This section shows that when the bootstrap voltage on VB(U) (VB(V), VB(W)) drops, the corresponding high side output

U (V, W) is switched off. When the voltage on VB(U) (VB(V), VB(W)) rises sufficiently, normal operation will resume.

4. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBTs are turned off. Normal operation

resumes later after the over−current condition is removed.

5. After VDD has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the LIN

input before enabling the driver for the HIN signal.

FAULT driven output

(with pull−up)

HIN

LIN

Upper IGBT

Gate Drive

VB(U), VB(V), VB(W)

VDD

VBS undervoltage protection reset signal

ITRIP

Automatic reset after protection(Fault−Output Pulse Width)

SD driven input

(with pull−up)

Lower IGBT

Gate Drive

Note 4

VIT < 0.44V

VIT w0.54V

VDD undervoltage protection reset voltage (Note 2)

VBS undervoltage protection reset voltage(Note 3)

Cross−conduction prevention period(Note 1)

HIN is disabled until LIN receives input (Note 5)

()

Table 5. INPUT / OUTPUT LOGIC TABLE

INPUT

OUTPUT

HIN

LIN

ITRIP

SD

High side IGBT

Low side IGBT

U,V,W

FAULT

H

L

L

H

ON (Note 5)

OFF

P

OFF

L

H

L

H

OFF

ON

NU,NV,NW

OFF

L

L

L

H

OFF

OFF

High Impedance

OFF

H

H

L

H

OFF

OFF

High Impedance

OFF

X

X

H

X

OFF

OFF

High Impedance

ON

X

X

L

L

OFF

OFF

High Impedance

OFF