STM32G071C8 datasheet(16/133 Pages) STMICROELECTRONICS

16 / 133 page

Functional overview

STM32G071x8/xB

16/133

DS12232 Rev 3

3.4

Embedded SRAM

STM32G071x8/xB devices have 32 Kbytes of embedded SRAM with parity. Hardware parity

check allows memory data errors to be detected, which contributes to increasing functional

safety of applications.

When the parity protection is not required because the application is not safety-critical, the

parity memory bits can be used as additional SRAM, to increase its total size to 36 Kbytes.

The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

3.5

Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot

options:

•

boot from User Flash memory

•

boot from System memory

•

boot from embedded SRAM

The boot pin is shared with a standard GPIO and can be enabled through the boot selector

option bit. The boot loader is located in System memory. It manages the Flash memory

reprogramming through USART on pins PA9/PA10, PC10/PC11 or PA2/PA3, through I2C-

bus on pins PB6/PB7 or PB10/PB11, or through SPI on pins PA4/PA5/PA6/PA7 or

PB12/PB13/PB14/PB15.

3.6

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link

time and stored at a given memory location.

3.7

Power supply management

3.7.1

Power supply schemes

The STM32G071x8/xB devices require a 1.7 V to 3.6 V operating supply voltage (VDD).

Several different power supplies are provided to specific peripherals:

•

VDD = 1.7 (1.6) to 3.6 V

VDD is the external power supply for the internal regulator and the system analog such

as reset, power management and internal clocks. It is provided externally through

VDD/VDDA pin.

The minimum voltage of 1.7 V corresponds to power-on reset release threshold

VPOR(max). Once this threshold is crossed and power-on reset is released, the

functionality is guaranteed down to power-down reset threshold VPDR(min).

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