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LIS25BA датащи(PDF) 16 Page - STMicroelectronics |
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LIS25BA датащи(HTML) 16 Page - STMicroelectronics |
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16 / 32 page ![]() TDM interface specifications LIS25BA 16/32 DocID031510 Rev 4 4.2 Frame synchronization (WCLK) The function of the WCLK is simply to identify the beginning of a frame. In particular the frame start at the rising edge of WCLK, and the WCLK widths supported are: 50% duty cycle One slot width (16 BCLK) One BCLK width In TDM mode, LIS25BA shall output accelerometer data on the SDOUT pin at the following sampling rates: WCLK = 8 kHz WCLK = 16 kHz WCLK = 24 kHz As depicted in Figure 6, the TDM input sampling rate (ODR_8kHz, ODR_16kHz and ODR_24kHz), and the associated data inputs (dataX_8kHz, dataX_16kHz, dataX_24kHz, dataY_8kHz, dataY_16kHz, dataY_24kHz, dataZ_8kHz, dataZ_16kHz and dataZ_24kHz ) can be selected in two different ways: 1. Using the I²C register wclk_fq (TDM_CTRL_REG (2Eh), bits 2 and 1). In this case the I²C register ODR_AUTO_EN (AXES_CTRL_REG (2Fh), bit 0) is equal to zero, that means that the ODR_auto functionality is disabled. 2. Using the output of the ODR_auto block (ODR_AUTO_EN (AXES_CTRL_REG (2Fh), bit 0) equal to one). This latter simply receives as inputs both the MCLK and the WCLK and it computes the current sampling frequency as a ratio between the MCLK and WCLK. The possible outputs of the ODR_auto block are: a) 00: sampling rate equal to 8 kHz (MCLK/WCLK = 1536) b) 01: sampling rate equal to 16 kHz (MCLK/WCLK = 768) c) 10: sampling rate equal to 24 kHz (MCLK/WCLK = 512) Observing Figure 6, it is possible to see, that if a ratio between MCLK and WCLK differ from 1536, 768 and 512, the sampling rate equal to 8 kHz is selected. 4.3 Serial clock (BCLK) The sole purpose of the serial clock BCLK is to shift the data out of the serial SDOUT port. To this purpose, the TDM interface uses an internal counter that is set to one when the rising edge of the WCLK is detected, and it is reset to zero when the maximum number of BCLK in a WCLK period is reached. The maximum number of BCLK contained in a WCLK period (cmax input of the TDM in Figure 6) can be expressed as a function of both the BCLK and WCLK frequencies, and can be computed using the following equation: Equation 1 |
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