XRT79L71IB datasheet(27/441 Pages) EXAR

27 / 441 page

áç

PRELIMINARY

XRT79L71

1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

REV. P1.0.3

TxGFCClk

Transmit GFC Nibble-Field Serial Input port - Clock Output signal:

This signal, along with TxGFC and TxGFCMSB combine to function as the

Transmit GFC Nibble-field serial input port. This output signal functions as the

demand clock signal for this port. The user will specify the value of the GFC

field, within a given ATM cell, by serially transmitting its four bit-value into the

TxGFC input pin. The Transmit GFC Nibble-Field serial input port will latch the

contents of TxGFC upon the rising edge of this clock signal. Hence, the local ter-

minal equipment should be designed to place its outbound GFC bits on to the

TxGFC line, upon the falling edge of this clock signal.

NOTE: This output pin is only active if the XRT79L71 has been configure to

operate in the ATM Mode.

TxNib_3/

TxPOHIns/

TxHDLCDat_3

Transmit Nibble Interface - Bit 3/Transmit PLCP Path Overhead Insert

enable/Transmit HDLC Controller Data Bus - Bit 3 input:

The function of this input pin depends upon whether the XRT79L71 is configured

to operate in the Clear-Channel Framer Mode, the High-Speed HDLC Controller

Mode or in the ATM/PLCP Mode.

Clear-Channel Framer Mode - TxNib_3:

If the XRT79L71 is configured to operate in the Nibble-Parallel Mode, then this

input pin will function as the bit 3 (MSB) input to the Transmit Nibble-Parallel input

interface. The Transmit Payload Data Input Interface block will sample this signal

(along with TxNib_0 through TxNib_2) upon the falling edge of TxNibClk.

NOTE: This input pin is inactive if the XRT79L71 is configured to operate in the

Serial Mode.

ATM/PLCP Mode - TxPOHIns:

f the XRT79L71 is configured to operate in the ATM Mode, and if (within the ATM

Mode, the chip is also configured to operate in the PLCP Mode), then this input

pin functions as the Transmit PLCP Path Overhead Port - Enable input pin. In

this mode, the user can externally insert desired path overhead byte values into

the outbound PLCP frames.

The Transmit PLCP Path Overhead Input port becomes active whenever the user

asserts this input pin by pulling it "High". Once this occurs, the data, residing

upon the TxPOH input pin will be sampled upon the rising edge of the TxPOHClk

signal.

This input pin is inactive if the XRT79L71 is configured to operate in the Direct-

Mapped ATM Mode.

High-Speed HDLC Controller Mode - TxHDLCDat_3:

If the XRT79L71 is configured to operate in the High-Speed HDLC Controller

mode, then the local terminal equipment will be provided with a byte-wide Trans-

mit HDLC Controller byte-wide input interface. This input pin will function as Bit 3

within this byte wide interface.

Data, residing on the Transmit HDLC Controller byte wide input interface, will be

sampled upon the rising edge of the TxHDLCClk output signal.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB датащи(PDF) 27 Page - Exar Corporation

XRT79L71IB датащи(HTML) 27 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL