SAMV71Q21 datasheet(9/41 Pages) MICROCHIP

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Module

Item and Feature

Summary

Affected Silicon

Revisions

QSPI

13.2 WDRBT

When the QSPI is in SPI mode, the

WDRBT feature is not functional.

RTC

14.1 RTC_CALR Reset

Value

On Revision A silicon, the reset value of

the RTC_CALR register is 0x01E11220.

SDRAMC

15.1 SDRAM Controller

Scrambling Use

Limitation

The scrambling/unscrambling feature of

the SDRAM Controller (SDRAMC) has a

use limitation.

SDRAMC

15.2 USB and SDRAM

Concurrent Access

Issue

USB module functionality is adversely

affected with concurrent SDRAM

access.

SMC

16.1 SMC_WPSR

Protection

When the write protection feature is

enabled and a write attempt into a

protected register is performed, the

Write Protection Violation Source

(WPVSRC) bit field in the SMC_WPSR

violation source.

SSC

17.1 Inverted Left/Right

Channels

When the SSC is in Slave mode, the TF

signal is derived from the codec and not

controlled by the SSC.

SSC

17.2 Unexpected TD

Output Delay

An unexpected delay on TD output may

occur when the SSC is configured under

certain conditions.

SUPC

18.1 Write-Protection

The SUPC_WUIR register is not write-

protected.

SUPC

18.2 Programmable

Clock Controller

Programmable Clock Outputs, PCK0–

PCK2, selected from the clock generator

outputs to drive the device PCK pins are

not supported and should not be used.

TWIHS

19.1 I2C Hold Timing

Incompatibility

The TWIHS module is not compatible

with I2C hold timing.

TWIHS

19.2 Clear Command

A bus reset using the CLEAR bit of the

TWIHS Control register does not work

correctly during a bus busy state.

USART

20.1 Flow Control with

DMA

The RTS signal is not connected to the

DMA. Therefore, when DMA is used,

Flow Control is not supported.

SAM E70/S70/V70/V71 Family

Silicon Issue Summary

Datasheet Errata

DS80000767C-page 9

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