XRT85L61

BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR

REV. 1.0.1

4

11

S1

I

Mode Select

are 1 RCLK wide.

12

S2

I

Mode Select

13

S3

I

Mode Select

14

NC

***

This pin must be grounded for normal operation

15

DATMUT

I

Data Muting:

Connect this pin “High” to mute data output to “Low” state at RPOS/

RNEG. The RLOS pin can be connected to this pin to mute the output

when RLOS occurs.

Ω resistor

16

RNEG

O

Receive Negative Data Output:

The data is half clock cycle wide.

17

RPOS

O

Receive Positive Data Output:

The data is half clock cycle wide

18

RCLK

O

Receive Clock Output

Outputs either 1.544 MHz or 2.048 MHz or 64 kHz clock

19

DGND

***

Digital Supply Ground

20

DVDD

***

Digital Supply Voltage (3.3V ± 5%)

21

RLOS

O

Receive Loss of Signal Output

22

400Hz

O

400 Hz Clock output for 64 kHz Operation

23

8 kHz

O

8 kHz clock output for 64 kHz Operation

24

400Hz_LCV

O

Line Code Violation for 400 Hz

This pin will stay “High” when 400 Hz is not in sync.

PIN DESCRIPTIONS

S2

S3

0

0

0

1

1

0

1

1

MODE

64 kHz + 8 kHz

64kHz+8kHz+400Hz

E1 RZ

E1 NRZ

S1

0

0

0

0

0

0

0

1

1

1

1

T1

Reserved

1

1

1

1

0