PCM4108CPAPT datasheet(19/39 Pages) TI

19 / 39 page

PCM4108

SBAS354 − JUNE 2005

www.ti.com

POWER-DOWN OPERATION

The PCM4108 can be forced to a power-down state by

applying a low level to the RST input for a minimum of

65,536 system clock cycles. In power-down mode, all

internal clocks are stopped, and analog outputs are set to

a high-impedance state. The system clock can then be

removed to conserve additional power. In the case of a

system clock restart when exiting the power-down state,

the clock should be restarted prior to a low-to-high

transition of the reset signal at the RST input. The

low-to-high transition of the reset signal initiates a reset

sequence, as described in the Reset Operation section of

this data sheet.

In Software mode, two additional power-down controls are

provided. The PDN12 and PDN34 bits are located in

Control Register 6 of Bank A and may be used to

power-down channel pairs, with PDN12 corresponding to

channels 1 and 2, and PDN34 corresponding to channels

3 and 4. The PDN56 and PDN78 bits are located in Control

channels 5 and 6, and PDN78 corresponding to channels

7 and 8. This design allows the user to conserve power

when a channel pair is not in use. The power-down

function is the same as described in the previous

paragraph for the corresponding channel pair. Unlike the

power-down function implemented using the RST input,

setting a power-down bit will immediately power down the

corresponding channel pair.

When exiting power-down mode, either by forcing the RST

input high or by setting the corresponding control bits low,

the analog outputs will transition from the high-impedance

state to the mute state, with the output level set to the

bipolar zero voltage. There may be a small transient

created by this transition, since an internal capacitor

charge can initially force the output to a voltage above or

below bipolar zero, or external circuitry can pull the outputs

to some other voltage level. Figure 8 illustrates the state of

the analog outputs before, during, and after a power-down

event.

Analog

Outputs

65,536

SCKI Periods

Outputs are On

Outputs are

Muted

RST

Analog

Outputs

1024

SCKI Periods

Required for

Initialization

1024

SCKI Periods

Required for

Initialization

Outputs are On

Outputs are

High Impedance

Outputs are

High Impedance

Outputs Transition

from High Impedance

to Muted State

Outputs Transition

from High Impedance

to Muted State

PDN12

PDN34

PDN56

PDN78

Outputs are On

Transitioning

to Driven State

Figure 8. Analog Output State for Power-Down Operations

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