PCM4108CPAPT datasheet(17/39 Pages) TI

17 / 39 page

PCM4108

SBAS354 − JUNE 2005

www.ti.com

SCKI

SCKIH

SCKIL

PARAMETER

DESCRIPTION

MIN

MAX

UNITS

System Clock Period

t SCKIH

System Clock High Pulse Time

tSCKIL

System Clock Low Pulse Time

t SCKI

Figure 4. System Clock Timing Requirements

RESET OPERATION

The PCM4108 includes three reset functions: power-on,

external, and software-controlled. This section describes

each of the three reset functions.

On power up, the internal reset signal is forced low, forcing

the PCM4108 into a reset state. The power-on reset circuit

monitors the VDD, VCC1, and VCC2 power supplies. When

VDD exceeds +2.0V (margin of error is ±400mV) and VCC1

and VCC2 exceed +4.0V (margin of error is ±400mV), the

internal reset signal is forced high. The PCM4108 then

waits for the system clock input (SCKI) to become active.

Once the system clock has been detected, the initialization

sequence begins. The initialization sequence requires

1024 system clock periods for completion. When the

initialization sequence is completed, the PCM4108 is

ready to accept audio data at the audio serial port. Figure 5

shows the power-on reset sequence timing.

If the PCM4108 is configured for Software mode control

via the SPI port, all control registers will be reset to their

default state during the initialization sequence. In both

Standalone and Software modes, the analog outputs for all

eight channels are muted during the reset and initialization

sequence. While in mute state, the analog output pins are

driven to the bipolar zero voltage, or VCC/2.

The user may force a reset initialization sequence at any

time while the system clock input is active by utilizing the

RST input (pin 13). The RST input is active low, and

requires a minimum low pulse width of 40ns. The

low-to-high transition of the applied reset signal will force

an initialization sequence to begin. As in the case of the

power-on reset, the initialization sequence requires 1024

system clock periods for completion. Figure 6 illustrates

the reset sequence initiated when using the RST input.

A reset initialization sequence is available in Software

mode, using the RST bit in Control Register 6. The RST bit

is active high. When RST is set to ‘1’, a reset sequence is

initiated in the same fashion as an external reset applied

at the RST input.

Figure 7 shows the state of the analog outputs for the

PCM4108 before, during and after the reset operations.

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