TDA7513T datasheet(20/59 Pages) STMICROELECTRONICS

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TDA7513T

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5.3.2 Frequency Generation for Phase Comparison

The VCO signal is fed to a two-modulus counter (32/33) prescaler, which is controlled by a 5-bit divider

(A). A 5-bit register (PC0 to PC4) controls this divider. The output of the prescaler is connected to an 11-

bit divider (B), controlled by an 11-bit PC register (PC5 to PC15).

The following expressions relate the divider output frequency (fSYN, forced by the loop to equal the refer-

ence frequency at the phase comparator input fREF) to the VCO frequency (fVCO) and to the crystal oscil-

lator frequency (fXTAL):

fXTAL = (R+1) x fREF

fVCO = [33 x A + (B + 1 - A) x 32] x fREF

fVCO = (32 x B + A + 32) x fREF

Important: For correct operation: A

≤32; B ≥A

5.3.3 Three State Phase Comparator

The phase comparator generates a phase error signal according to phase difference between fSYN and

fREF. This phase error signal drives the charge pump current generator.

5.3.4 Charge Pump Current Generator

This system generates correction current pulses with a polarity and a duration dictated by the phase error

signal. The current absolute values are programmable through register A for high current and register B

for low current.

The charge pump operates in high current mode when the phase difference between between fSYN and

fREF is high. The switch back to low current mode can be done either automatically as a function of the

inlock detector output (setting bit LDENA to "1") or via software.

After reaching a phase difference equivalent to 10-40 ns (programmable) and a delay multiple of 1/fREF,

the chargepump is forced in low current mode. A new PLL divider programming by I2C bus will switch the

chargepump into high current mode.

A few programmable phase errors (D0, D1) are available for inlock detection. The count of detected inlock

informations to release the inlock signal is adjustable (D2, D3), to avoid switching to low current during a

frequency jump.

5.3.5 Low Noise CMOS Op-amp

An internal voltage divider at pin #LFREF is connected to the positive input of the low noise op-amp. The

charge pump output is connected to the negative input. This internal amplifier in cooperation with external

components provides the active loop filter. Only one loop filter connection is provided because the same

reference frequency is used for both AM and FM operation. The pin #LFHC is connected in such a way

as to partially shunt the loop filter in order to decrease the time constant of the filter itself during jumps with

high current mode activated.

5.3.6 IF Counter Block

The input signal for FM and AM has the same structure although FM IF is measured at IF1 (10.7MHz) and

AM IF is measured at IF2 (450kHz). The degree of integration is adjustable to up to eight different mea-

suring cycle times. The tolerance of the accepted count value is adjustable to reach the optimum compro-

mise between search speed and evaluation precision.

T center frequency of the measured count value is adjustable to fit the IF-filter tolerance.

5.3.7 The IF-Counter Mode

The IF counter works in 2 modes controlled by the IFCM register.

5.3.8 Sampling Timer

A 14-bit programmable (IRC) sampling timer generates the gate signal for the main counter. In FM mode

a 6.25kHz frequency reference is generated for this purpose, whereas in AM mode this reference be-

comes 1kHz. These reference frequencies are further divided to generate the measurement time windows

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