AM79C930VCW datasheet(131/161 Pages) AMD

131 / 161 page

P R E L I M I N A R Y

AMD

131

Am79C930

AC CHARACTERISTICS

5.0 AND 3.3 V PCMCIA INTERFACE

ABSOLUTE MAXIMUM RATINGS

Storage Temperature:

–65 to +150*C

. . . . . . . . . . . .

Ambient Temperature Under Bias:

–65 to +125*C

. . .

Supply Voltage to AVSS

or DVSS (AVDD, DVDD):

–0.3 to +6 V

. . . . . . . . . . . . . .

Stresses above those listed under Absolute Maximum

Ratings may cause permanent device failure. Functionality at

or above these limits is not implied. Exposure to Absolute

Maximum

Ratings

for

extended

periods

may

affect

device reliability.

OPERATING RANGES

Commercial (C) Devices

Temperature (TA)0

°C to + 70°C

. . . . . . . . . . . . . . . . .

Supply Voltages (VCC, VDDT, VDDU1, VDDU2, VDDM, VDDP)

3.0 V to 5.25 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply Voltages

(AVDD, VDD5)

+5 V

± 5%

. . . . . . . . . . . . . . . . . . . . . . . .

All inputs within the range: VSS – 0.5 V

≤ V

+ 0.1 X

VDD – where VSS and VDD are appropriate reference pins

for a given input pin. (See section on power supply

pin descriptions.)

CL = 50 pF unless otherwise noted

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

PCMCIA MEMORY READ ACCESS

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

tAVQV

Address access time

Note 1

550

tAVGL

Address setup to

↓

5ns

tGHAX

Address hold from

↑

tELQV

CE access time

Note 1

550

tELGL

CE setup to OE

↓

0ns

tGHEH

CE hold from OE

↑ (READ) or

CE hold from WE

↑ (WRITE)

tGLQV

OE acess time

Note 1

200

tGLWTV

WAIT valid from OE

↓

tWTLWTH

WAIT pulse width

Notes 2, 3

53 X TCLKIN

tGLQNZ

Data Bus driven from

Note 3

tQVWTH

Data setup to

WAIT

↑

0ns

tGHQZ

Data disabled from

↑

Note 3

Notes:

1. Assumes no wait state access is programmed.

2. The max value for this parameter assumes the following worst case situation:

Value

Worst Case

FLASH and SRAM wait states set at “3.”

Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins

instruction fetch cycle to FLASH memory.

PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188

controller access.

Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.

After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;

PCMCIA READ stycle is being held in wait state.

After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.

After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed onto

memory bus to SRAM; host is still held in wait state.

At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.

3. Parameter is not included in production test.

AM79C930VCW датащи(PDF) 131 Page - Advanced Micro Devices

AM79C930VCW датащи(HTML) 131 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL